Datasheet

SATA Controller Registers (D31:F5)
372 Intel® Xeon® Processor D-1500 Product Family
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
Note: Intel® Xeon® Processor D-1500 Product Family SATA controller is not arbitrated as a PCI device;
therefore, it does not need a master latency timer.
9.1.1 VID—Vendor Identification Register (SATA—D31:F5)
Offset Address: 00h–01h Attribute: RO
Default Value: 8086h Size: 16 bit
Lockable: No Power Well: Core
9.1.2 DID—Device Identification Register (SATA—D31:F5)
Offset Address: 02h–03h Attribute: RO
Default Value: See bit description Size: 16 bit
Lockable: No Power Well: Core
9.1.3 PCICMD—PCI Command Register (SATA–D31:F5)
Address Offset: 04h–05h Attribute: RO, R/W
Default Value: 0000h Size: 16 bits
90h–91h MAP Address Map 0000h R/W
92h–93h PCS Port Control and Status 0000h R/W, RO,
R/WC
A8h–ABh SATACR0 SATA Capability Register 0 0010B012h RO, R/WO
ACh–AFh SATACR1 SATA Capability Register 1 00000048h RO
B0h–B1h FLRCID FLR Capability ID 0009h RO
B2h–B3h FLRCLV FLR Capability Length and Value 2006h RO
B4h–B5h FLRCTRL FLR Control 0000h R/W, RO
C0h ATC APM Trapping Control 00h R/W
C4h ATS APM Trapping Status 00h R/WC
Table 9-1. SATA Controller PCI Register Address Map (SATA–D31:F5) (Sheet 2 of 2)
Offset Mnemonic Register Name Default Attribute
Bit Description
15:0 Vendor ID — RO. This is a 16-bit value assigned to Intel. Intel VID = 8086h
Bit Description
15:0 Device ID — RO. This is a 16-bit value assigned to Intel® Xeon® Processor D-1500 Product Family
SATA controller.
Note: The value of this field will change dependent upon the value of the MAP Register.
Bit Description
15:11 Reserved
10 Interrupt Disable — R/W. This disables pin-based INTx# interrupts. This bit has no effect on MSI
operation.
0 = Internal INTx# messages are generated if there is an interrupt and MSI is not enabled.
1 = Internal INTx# messages will not be generated.
9 Fast Back to Back Enable (FBE) — RO. Hardwired to 0.
8 SERR# Enable (SERR_EN) — RO. Hardwired to 0.
7 Wait Cycle Control (WCC) — RO. Hardwired to 0.
6 Parity Error Response (PER) — R/W.
0 = Disabled. SATA controller will not generate PERR# when a data parity error is detected.
1 = Enabled. SATA controller will generate PERR# when a data parity error is detected.