Datasheet

Intel® Xeon® Processor D-1500 Product Family and System Clocks
Intel® Xeon® Processor D-1500 Product Family 37
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
2.3 Functional Blocks
Intel® Xeon® Processor D-1500 Product Family has 1 main PLL in which its output is
divided down through Modulators and Dividers to provide great flexibility in clock
source selection, configuration, and better power management. Ta b le 2-3 describes the
PLLs on Intel® Xeon® Processor D-1500 Product Family and the clock domains that are
driven from the PLLs.
Notes:
1. Indicates the source clock frequencies driven to other internal logic for delivering functionality needed.
Does not indicate external outputs.
Spread Spectrum adjustment can be made without platform reboot. Tabl e 2- 4 provides
a basic description of spread modulators that operate on the XCK PLL’s 2.7 GHz
outputs.
2.4 Clock Configuration Access Overview
Intel® Xeon® Processor D-1500 Product Family provides increased flexibility of host
equivalent configurability of clocks, using Intel ME FW.
In the Intel ME FW assisted configuration mode, control settings for PLLs, Spread
Modulators, and other clock configuration registers will be handled by the Intel ME. The
parameters to be loaded will reside in the Intel ME data region of the SPI Flash device.
BIOS would only have access to the register set through a set of Intel
MEI commands
to the Intel ME.
Table 2-3. Intel® Xeon® Processor D-1500 Product Family PLLs
PLL Outputs
1
Description/Usage
XCK_PLL Four 2.7 GHz outputs 90° apart. Outputs are
routed to each of the Spread Modulator blocks
before hitting the various dividers and the other
PLLs to provide clocks to all of the I/O interface
logic. This PLL also provides 5.4 GHz and
2.7 GHz CMOS outputs for use by various
dividers to create non-spread output clocks.
Main Reference PLL. Always enabled in
Integrated Clocking mode. Resides in
core power well and is not powered in
S3 and below states. Powered in sub-S0
states by a Suspend well Ring oscillator.
Table 2-4. Modulator Blocks
Modulator Description
MOD1 Used for spread modulation, or bending, on 135 MHz clock to integrated graphics display.
Typical display usage model is 0.5% down-spread. In certain usage case, this modulator
can be shut off for 0% spread with or without clock bending. Used by the display driver
only.
MOD2 Used for spread modulation and fine grain frequency synthesis on nominal 100 MHz
overclockable clock to PEG. This modulator also subject to adaptive clocking adjustment
(for EMC) when left on at nominal 100 MHz frequency.
MOD3 Used for spread modulation (and adaptive clocking) on 100 M Hz clock to processor PEG,
PCIe*, USB 3.0, SATA, Single Ended 33 MHz, and Thermal Sensor.
MOD4 Used for fine grain frequency synthesis on nominal 135 MHz, non-spread clock to
integrated graphics display. Used by the display driver only.
MOD5 Used for fine grain frequency synthesis of a wide variety of integrated graphics display
VGA clocking needs. Used by the display driver only.
MOD6 Used for fine grain frequency synthesis of 96 MHz non-spread clock to USB PLL and Intel®
Xeon® Processor D-1500 Product Family logic. 48/24 MHz to Flex Clocks are further
derived from 96 MHz output.
MOD7 Used for fine grain frequency synthesis of 14.31818 MHz non-spread clock to Flex Clocks
and Intel® Xeon® Processor D-1500 Product Family logic.