Datasheet

SATA Controller Registers (D31:F2)
Intel® Xeon® Processor D-1500 Product Family 369
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
8.4.2.13 PxSACT—Port [5:0] Serial ATA Active Register (D31:F2)
Address Offset: Port 0: ABAR + 134h Attribute: R/W
Port 1: ABAR + 1B4h
Port 2: ABAR + 234h (if port available; see Section 1.3)
Port 3: ABAR + 2B4h (if port available; see Section 1.3)
Port 4: ABAR + 334h
Port 5: ABAR + 3B4h
Default Value: 00000000h Size: 32 bits
8.4.2.14 PxCI—Port [5:0] Command Issue Register (D31:F2)
Address Offset: Port 0: ABAR + 138h Attribute: R/W
Port 1: ABAR + 1B8h
Port 2: ABAR + 238h (if port available; see Section 1.3)
Port 3: ABAR + 2B8h (if port available; see Section 1.3)
Port 4: ABAR + 338h
Port 5: ABAR + 3B8h
Default Value: 00000000h Size: 32 bits
Bit Description
31:0 Device Status (DS) — R/W. System software sets this bit for SATA queuing operations prior to
setting the PxCI.CI bit in the same command slot entry. This field is cleared using the Set Device Bits
FIS.
This field is also cleared when PxCMD.ST (ABAR+118h/198h/218h/298h:bit 0) is cleared by
software, and as a result of a COMRESET or SRST.
Bit Description
31:0 Commands Issued (CI) — R/W. This field is set by software to indicate to Intel® Xeon® Processor
D-1500 Product Family that a command has been built-in system memory for a command slot and
may be sent to the device. When Intel® Xeon® Processor D-1500 Product Family receives a FIS
which clears the BSY and DRQ bits for the command, it clears the corresponding bit in this register
for that command slot. Bits in this field shall only be set to 1 by software when PxCMD.ST is set to 1.
This field is also cleared when PxCMD.ST (ABAR+118h/198h/218h/298h:bit 0) is cleared by
software.