Datasheet

SATA Controller Registers (D31:F2)
Intel® Xeon® Processor D-1500 Product Family 367
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
8.4.2.12 PxSERR—Port [5:0] Serial ATA Error Register (D31:F2)
Address Offset: Port 0: ABAR + 130h Attribute: R/WC
Port 1: ABAR + 1B0h
Port 2: ABAR + 230h (if port available; see Section 1.3)
Port 3: ABAR + 2B0h (if port available; see Section 1.3)
Port 4: ABAR + 330h
Port 5: ABAR + 3B0h
Default Value: 00000000h Size: 32 bits
Bits 26:16 of this register contain diagnostic error information for use by diagnostic
software in validating correct operation or isolating failure modes. Bits 11:0 contain
error information used by host software in determining the appropriate response to the
error condition. If one or more of bits 11:8 of this register are set, the controller will
stop the current transfer.
11:8 Interface Power Management Transitions Allowed (IPM) — R/W. Indicates which power states
Intel® Xeon® Processor D-1500 Product Family is allowed to transition to:
All other values reserved
7:4 Speed Allowed (SPD) — R/W. Indicates the highest allowable speed of the interface. This speed is
limited by the CAP.ISS (ABAR+00h:bit 23:20) field.
Intel® Xeon® Processor D-1500 Product Family Supports Gen 1 communication rates (1.5 Gb/s),
Gen 2 rates (3.0 Gb/s) and Gen 3 rates (6.0 Gb/s). If software changes SPD after port has been
enabled, software is required to perform a port reset using DET=1h. This field shall remain 1h until
set to another value by software.
3:0 Device Detection Initialization (DET) — R/W. Controls Intel® Xeon® Processor D-1500 Product
Family’s device detection and interface initialization.
All other values reserved.
When this field is written to a 1h, Intel® Xeon® Processor D-1500 Product Family initiates
COMRESET and starts the initialization process. When the initialization is complete, this field shall
remain 1h until set to another value by software.
This field may only be changed to 1h or 4h when PxCMD.ST is 0. Changing this field while Intel®
Xeon® Processor D-1500 Product Family is running results in undefined behavior.
Note: It is permissible to implement any of the Serial ATA defined behaviors for transmission of
COMRESET when DET=1h.
Bit Description
Value Description
0h No interface restrictions
1h Transitions to the PARTIAL state disabled
2h Transitions to the SLUMBER state disabled
3h Transitions to both PARTIAL and SLUMBER states disabled
Value Description
0h No speed negotiation restrictions
1h Limit speed negotiation to Generation 1 communication rate
2h Limit speed negotiation to Generation 2 communication rate
3h Limit speed negotiation to Generation 3 communication rate
Value Description
0h No device detection or initialization action requested
1h Perform interface communication initialization sequence to establish
communication. This is functionally equivalent to a hard reset and results in
the interface being reset and communications re-initialized
4h Disable the Serial ATA interface and put Phy in offline mode