Datasheet

SATA Controller Registers (D31:F2)
Intel® Xeon® Processor D-1500 Product Family 365
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
8.4.2.9 PxSIG—Port [5:0] Signature Register (D31:F2)
Address Offset: Port 0: ABAR + 124h Attribute: RO
Port 1: ABAR + 1A4h
Port 2: ABAR + 224h (if port available; see Section 1.3)
Port 3: ABAR + 2A4h (if port available; see Section 1.3)
Port 4: ABAR + 324h
Port 5: ABAR + 3A4h
Default Value: FFFFFFFFh Size: 32 bits
This is a 32-bit register which contains the initial signature of an attached device when
the first D2H Register FIS is received from that device. It is updated once after a reset
sequence.
8.4.2.10 PxSSTS—Port [5:0] Serial ATA Status Register (D31:F2)
Address Offset: Port 0: ABAR + 128h Attribute: RO
Port 1: ABAR + 1A8h
Port 2: ABAR + 228h (if port available; see Section 1.3)
Port 3: ABAR + 2A8h (if port available; see Section 1.3)
Port 4: ABAR + 328h
Port 5: ABAR + 3A8h
Default Value: 00000000h Size: 32 bits
This is a 32-bit register that conveys the current state of the interface and host. Intel®
Xeon® Processor D-1500 Product Family updates it continuously and asynchronously.
When Intel® Xeon® Processor D-1500 Product Family transmits a COMRESET to the
device, this register is updated to its reset values.
7:0 Status (STS) — RO. Contains the latest copy of the task file status register. Fields in this register
that affect AHCI.
Bit Description
Bit Field Definition
7 BSY Indicates the interface is busy
6:4 N/A Not applicable
3 DRQ Indicates a data transfer is requested
2:1 N/A Not applicable
0 ERR Indicates an error during the transfer
Bit Description
31:0 Signature (SIG) — RO. Contains the signature received from a device on the first D2H register FIS.
The bit order is as follows:
Bit Field
31:24 LBA High Register
23:16 LBA Mid Register
15:8 LBA Low Register
7:0 Sector Count Register
Bit Description
31:12 Reserved