Datasheet
SATA Controller Registers (D31:F2)
364 Intel® Xeon® Processor D-1500 Product Family
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
8.4.2.8 PxTFD—Port [5:0] Task File Data Register (D31:F2)
Address Offset: Port 0: ABAR + 120h Attribute: RO
Port 1: ABAR + 1A0h
Port 2: ABAR + 220h (if port available; see Section 1.3)
Port 3: ABAR + 2A0h (if port available; see Section 1.3)
Port 4: ABAR + 320h
Port 5: ABAR + 3A0h
Default Value: 0000007Fh Size: 32 bits
This is a 32-bit register that copies specific fields of the task file when FISes are
received. The FISes that contain this information are: D2H Register FIS,PIO Setup FIS
and Set Device Bits FIS
12:8 Current Command Slot (CCS) — RO. Indicates the current command slot Intel® Xeon®
Processor D-1500 Product Family is processing. This field is valid when the ST bit is set in this
register, and is constantly updated by Intel® Xeon® Processor D-1500 Product Family. This field
can be updated as soon as Intel® Xeon® Processor D-1500 Product Family recognizes an active
command slot, or at some point soon after when it begins processing the command.
This field is used by software to determine the current command issue location of Intel® Xeon®
Processor D-1500 Product Family. In queued mode, software shall not use this field, as its value
does not represent the current command being executed. Software shall only use PxCI and
PxSACT when running queued commands.
7:5 Reserved
4 FIS Receive Enable (FRE) — R/W. When set, Intel® Xeon® Processor D-1500 Product Family
may post received FISes into the FIS receive area pointed to by PxFB (ABAR+108h/188h/208h/
288h) and PxFBU (ABAR+10Ch/18Ch/20Ch/28Ch). When cleared, received FISes are not accepted
by Intel® Xeon® Processor D-1500 Product Family, except for the first D2H (device-to-host)
register FIS after the initialization sequence.
System software must not set this bit until PxFB (PxFBU) have been programmed with a valid
pointer to the FIS receive area, and if software wishes to move the base, this bit must first be
cleared, and software must wait for the FR bit (bit 14) in this register to be cleared.
3 Command List Override (CLO) — R/W. Setting this bit to 1 causes PxTFD.STS.BSY and
PxTFD.STS.DRQ to be cleared to 0. This allows a software reset to be transmitted to the device
regardless of whether the BSY and DRQ bits are still set in the PxTFD.STS register. The Controller
sets this bit to 0 when PxTFD.STS.BSY and PxTFD.STS.DRQ have been cleared to 0. A write to this
register with a value of 0 shall have no effect.
This bit shall only be set to 1 immediately prior to setting the PxCMD.ST bit to 1 from a previous
value of 0. Setting this bit to 1 at any other time is not supported and will result in indeterminate
behavior. Software must wait for CLO to be cleared to 0 before setting PxCMD.ST to 1.
2 Power On Device (POD) — RO. Cold presence detect not supported. Defaults to 1.
1 Spin-Up Device (SUD) — R/W / RO
This bit is R/W and defaults to 0 for systems that support staggered spin-up (R/W when CAP.SSS
(ABAR+00h:bit 27) is 1). Bit is RO 1 for systems that do not support staggered spin-up (when
CAP.SSS is 0).
0 = No action.
1 = On an edge detect from 0 to 1, Intel® Xeon® Processor D-1500 Product Family starts a
COMRESET initialization sequence to the device.
Clearing this bit to 0 does not cause any OOB signal to be sent on the interface. When this bit is
cleared to 0 and PxSCTL.DET=0h, the controller will enter listen mode.
0 Start (ST) — R/W. When set, Intel® Xeon® Processor D-1500 Product Family may process the
command list. When cleared, Intel® Xeon® Processor D-1500 Product Family may not process the
command list. Whenever this bit is changed from a 0 to a 1, Intel® Xeon® Processor D-1500
Product Family starts processing the command list at entry 0. Whenever this bit is changed from a
1 to a 0, the PxCI register is cleared by Intel® Xeon® Processor D-1500 Product Family upon
Intel® Xeon® Processor D-1500 Product Family putting the controller into an idle state.
Refer to Section 10.3 of the Serial ATA AHCI Specification for important restrictions on when ST
can be set to 1 and cleared to 0.
Bit Description
Bit Description
31:16 Reserved
15:8 Error (ERR) — RO. Contains the latest copy of the task file error register.