Datasheet

SATA Controller Registers (D31:F2)
Intel® Xeon® Processor D-1500 Product Family 363
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
27 Aggressive Slumber / Partial (ASP) — R/W. When set to 1, and the ALPE bit (bit 26) is set,
Intel® Xeon® Processor D-1500 Product Family shall aggressively enter the slumber state when it
clears the PxCI register and the PxSACT register is cleared. When cleared, and the ALPE bit is set,
Intel® Xeon® Processor D-1500 Product Family will aggressively enter the partial state when it
clears the PxCI register and the PxSACT register is cleared. If CAP.SALP is cleared to 0, software
shall treat this bit as reserved.
26 Aggressive Link Power Management Enable (ALPE) — R/W. When set to 1, Intel® Xeon®
Processor D-1500 Product Family will aggressively enter a lower link power state (partial or
slumber) based upon the setting of the ASP bit (bit 27).
25 Drive LED on ATAPI Enable (DLAE) — R/W. When set to 1, Intel® Xeon® Processor D-1500
Product Family will drive the LED pin active for ATAPI commands (PxCLB[CHz.A] set) in addition to
ATA commands. When cleared, Intel® Xeon® Processor D-1500 Product Family will only drive the
LED pin active for ATA commands. See Section 3.15.9 for details on the activity LED.
24 Device is ATAPI (ATAPI) — R/W. When set to 1, the connected device is an ATAPI device. This
bit is used by Intel® Xeon® Processor D-1500 Product Family to control whether or not to
generate the server LED when commands are active. See Section 3.15.9 for details on the activity
LED.
23 Automatic Partial Slumber Transitions Enabled (APSTE)— R/W.
0 = This port will not perform Automatic Partial to Slumber Transitions.
1 = The HBA may perform Automatic Partial to Slumber Transitions.
Note: Software should only set this bit to ‘1’ if CAP2.APST is set to ‘1’.
22 Reserved
21 External SATA Port (ESP) — R/WO.
0 = This port supports internal SATA devices only.
1 = This port will be used with an external SATA device and Hot-Plug is supported. When set,
CAP.SXS must also be set.
This bit is not reset by Function Level Reset.
20 Reserved
19 Mechanical Switch Attached to Port (MPSP) — R/WO. If set to 1, Intel® Xeon® Processor D-
1500 Product Family supports a mechanical presence switch attached to this port.
Intel® Xeon® Processor D-1500 Product Family takes no action on the state of this bit – it is for
system software only. For example, if this bit is cleared, and an mechanical presence switch
toggles, Intel® Xeon® Processor D-1500 Product Family still treats it as a proper mechanical
presence switch event.
Note: This bit is not reset on a Controller reset or by a Function Level Reset.
18 Hot-Plug Capable Port (HPCP) — R/WO.
0 = Port is not capable of Hot-Plug.
1 = Port is Hot-Plug capable.
This indicates whether the platform exposes this port to a device which can be Hot-Plugged. SATA
by definition is hot-pluggable, but not all platforms are constructed to allow the device to be
removed (it may be screwed into the chassis, for example). This bit can be used by system
software to indicate a feature such as “eject device” to the end-user. Intel® Xeon® Processor D-
1500 Product Family takes no action on the state of this bit — it is for system software only. For
example, if this bit is cleared, and a Hot-Plug event occurs, Intel® Xeon® Processor D-1500
Product Family still treats it as a proper Hot-Plug event.
Note: This bit is not reset on a Controller reset or by a Function Level Reset.
17:16 Reserved
15 Controller Running (CR) — RO. When this bit is set, the DMA engines for a port are running.
14 FIS Receive Running (FR) — RO. When set, the FIS Receive DMA engine for the port is running.
13 Mechanical Presence Switch State (MPSS) — RO. The MPSS bit reports the state of a
mechanical presence switch attached to this port. If CAP.SMPS is set to 1 and the mechanical
presence switch is closed then this bit is cleared to 0. If CAP.SMPS is set to 1 and the mechanical
presence switch is open then this bit is set to 1. If CAP.SMPS is set to '0' then this bit is cleared to
0. Software should only use this bit if both CAP.SMPS and PxCMD.MPSP are set to 1.
Bit Description