Datasheet

SATA Controller Registers (D31:F2)
362 Intel® Xeon® Processor D-1500 Product Family
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
8.4.2.7 PxCMD—Port [5:0] Command Register (D31:F2)
Address Offset: Port 0: ABAR + 118h Attribute: R/W, RO, R/WO
Port 1: ABAR + 198h
Port 2: ABAR + 218h (if port available; see Section 1.3)
Port 3: ABAR + 298h (if port available; see Section 1.3)
Port 4: ABAR + 318h
Port 5: ABAR + 398h
Default Value: 0000w00wh Size: 32 bits
where w = 00?0b (for?, see bit description)
Function Level Reset:No (Bit 21, 19 and 18 only)
7 Device Interlock Enable (DIE) — R/W. When set, and PxIS.DIS is set, Intel® Xeon® Processor D-
1500 Product Family will generate an interrupt.
For systems that do not support an mechanical presence switch, this bit shall be a read-only 0.
6 Port Change Interrupt Enable (PCE) — R/W. When set, and GHC.IE and PxS.PCS are set, Intel®
Xeon® Processor D-1500 Product Family will generate an interrupt.
5 Descriptor Processed Interrupt Enable (DPE) — R/W. When set, and GHC.IE and PxS.DPS are
set, Intel® Xeon® Processor D-1500 Product Family will generate an interrupt.
4 Unknown FIS Interrupt Enable (UFIE) — R/W. When set, and GHC.IE is set and an unknown FIS
is received, Intel® Xeon® Processor D-1500 Product Family will generate this interrupt.
3 Set Device Bits FIS Interrupt Enable (SdBE) — R/W. When set, and GHC.IE and PxS.SdBS are
set, Intel® Xeon® Processor D-1500 Product Family will generate an interrupt.
2 DMA Setup FIS Interrupt Enable (DSE) — R/W. When set, and GHC.IE and PxS.DSS are set,
Intel® Xeon® Processor D-1500 Product Family will generate an interrupt.
1 PIO Setup FIS Interrupt Enable (PSE) — R/W. When set, and GHC.IE and PxS.PSS are set,
Intel® Xeon® Processor D-1500 Product Family will generate an interrupt.
0 Device to Host Register FIS Interrupt Enable (DHRE) — R/W. When set, and GHC.IE and
PxS.DHRS are set, Intel® Xeon® Processor D-1500 Product Family will generate an interrupt.
Bit Description
Bit Description
31:28 Interface Communication Control (ICC) — R/W.This is a four bit field that can be used to
control reset and power states of the interface. Writes to this field will cause actions on the
interface, either as primitives or an OOB sequence, and the resulting status of the interface will be
reported in the PxSSTS register (Address offset Port 0:ABAR+124h, Port 1: ABAR+1A4h, Port 2:
ABAR+224h, Port 3: ABAR+2A4h, Port 4: ABAR+224h, Port 5: ABAR+2A4h).
When system software writes a non-reserved value other than No-Op (0h), Intel® Xeon®
Processor D-1500 Product Family will perform the action and update this field back to Idle (0h).
If software writes to this field to change the state to a state the link is already in (such as,
interface is in the active state and a request is made to go to the active state), Intel® Xeon®
Processor D-1500 Product Family will take no action and return this field to Idle.
Note: When the ALPE bit (bit 26) is set, this register should not be set to 02h or 06h.
Value Definition
Fh–7h Reserved
6h Slumber: This will cause Intel® Xeon® Processor D-1500 Product Family to
request a transition of the interface to the slumber state. The SATA device may
reject the request and the interface will remain in its current state
5h–3h Reserved
2h Partial: This will cause Intel® Xeon® Processor D-1500 Product Family to
request a transition of the interface to the partial state. The SATA device may
reject the request and the interface will remain in its current state.
1h Active: This will cause Intel® Xeon® Processor D-1500 Product Family to
request a transition of the interface into the active
0h No-Op / Idle: When software reads this value, it indicates Intel® Xeon®
Processor D-1500 Product Family is not in the process of changing the
interface state or sending a device reset, and a new link command may be
issued.