Datasheet
SATA Controller Registers (D31:F2)
Intel® Xeon® Processor D-1500 Product Family 361
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
8.4.2.6 PxIE—Port [5:0] Interrupt Enable Register (D31:F2)
Address Offset: Port 0: ABAR + 114h Attribute: R/W, RO
Port 1: ABAR + 194h
Port 2: ABAR + 214h (if port available; see Section 1.3)
Port 3: ABAR + 294h (if port available; see Section 1.3)
Port 4: ABAR + 314h
Port 5: ABAR + 394h
Default Value: 00000000h Size: 32 bits
This register enables and disables the reporting of the corresponding interrupt to
system software. When a bit is set (1) and the corresponding interrupt condition is
active, then an interrupt is generated. Interrupt sources that are disabled (0) are still
reflected in the status registers.
6 Port Connect Change Status (PCS) — RO. This bit reflects the state of PxSERR.DIAG.X.
(ABAR+130h/1D0h/230h/2D0h, bit 26) Unlike other bits in this register, this bit is only cleared when
PxSERR.DIAG.X is cleared.
0 = No change in Current Connect Status.
1 = Change in Current Connect Status.
5 Descriptor Processed (DPS) — R/WC. A PRD with the I bit set has transferred all its data.
4 Unknown FIS Interrupt (UFS) — RO. When set to 1, this bit indicates that an unknown FIS was
received and has been copied into system memory. This bit is cleared to 0 by software clearing the
PxSERR.DIAG.F bit to 0. This bit does not directly reflect the PxSERR.DIAG.F bit. PxSERR.DIAG.F is
set immediately when an unknown FIS is detected, whereas this bit is set when the FIS is posted to
memory. Software should wait to act on an unknown FIS until this bit is set to 1 or the two bits may
become out of sync.
3 Set Device Bits Interrupt (SdBS) — R/WC. A Set Device Bits FIS has been received with the I bit
set and has been copied into system memory.
2 DMA Setup FIS Interrupt (DSS) — R/WC. A DMA Setup FIS has been received with the I bit set
and has been copied into system memory.
1 PIO Setup FIS Interrupt (PSS) — R/WC. A PIO Setup FIS has been received with the I bit set, it
has been copied into system memory, and the data related to that FIS has been transferred.
0 Device to Host Register FIS Interrupt (DHRS) — R/WC. A D2H Register FIS has been received
with the I bit set, and has been copied into system memory.
Bit Description
Bit Description
31 Cold Presence Detect Enable (CPDE) — RO. Cold Presence Detect is not supported.
30 Task File Error Enable (TFEE) — R/W. When set, and GHC.IE and PxTFD.STS.ERR (due to a
reception of the error register from a received FIS) are set, Intel® Xeon® Processor D-1500 Product
Family will generate an interrupt.
29 Host Bus Fatal Error Enable (HBFE) — R/W. When set, and GHC.IE and PxS.HBFS are set, Intel®
Xeon® Processor D-1500 Product Family will generate an interrupt.
28 Host Bus Data Error Enable (HBDE) — R/W. When set, and GHC.IE and PxS.HBDS are set, Intel®
Xeon® Processor D-1500 Product Family will generate an interrupt.
27 Host Bus Data Error Enable (HBDE) — R/W. When set, GHC.IE is set, and PxIS.HBDS is set,
Intel® Xeon® Processor D-1500 Product Family will generate an interrupt.
26 Interface Non-fatal Error Enable (INFE) — R/W. When set, GHC.IE is set, and PxIS.INFS is set,
Intel® Xeon® Processor D-1500 Product Family will generate an interrupt.
25 Reserved
24 Overflow Error Enable (OFE) — R/W. When set, and GHC.IE and PxS.OFS are set, Intel® Xeon®
Processor D-1500 Product Family will generate an interrupt.
23 Incorrect Port Multiplier Enable (IPME) — R/W. Intel® Xeon® Processor D-1500 Product Family
SATA controller does not support Port Multipliers. BIOS and storage software should keep this bit
cleared to 0.
22 PhyRdy Change Interrupt Enable (PRCE) — R/W. When set, and GHC.IE is set, and PxIS.PRCS is
set, Intel® Xeon® Processor D-1500 Product Family shall generate an interrupt.
21:8 Reserved