Datasheet

SATA Controller Registers (D31:F2)
360 Intel® Xeon® Processor D-1500 Product Family
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
8.4.2.4 PxFBU—Port [5:0] FIS Base Address Upper 32-Bits Register (D31:F2)
Address Offset: Port 0: ABAR + 10Ch Attribute: R/W
Port 1: ABAR + 18Ch
Port 2: ABAR + 20Ch (if port available; see Section 1.3)
Port 3: ABAR + 28Ch (if port available; see Section 1.3)
Port 4: ABAR + 30Ch
Port 5: ABAR + 38Ch
Default Value: Undefined Size: 32 bits
8.4.2.5 PxIS—Port [5:0] Interrupt Status Register (D31:F2)
Address Offset: Port 0: ABAR + 110h Attribute: R/WC, RO
Port 1: ABAR + 190h
Port 2: ABAR + 210h (if port available; see Section 1.3)
Port 3: ABAR + 290h (if port available; see Section 1.3)
Port 4: ABAR + 310h
Port 5: ABAR + 390h
Default Value: 00000000h Size: 32 bits
Bit Description
31:0 FIS Base Address Upper (FBU) — R/W. Indicates the upper 32-bits for the received FIS base for
this port.
These bits are not reset on a controller reset.
Bit Description
31 Cold Port Detect Status (CPDS) — RO. Cold presence detect is not supported.
30 Task File Error Status (TFES) — R/WC. This bit is set whenever the status register is updated by
the device and the error bit (PxTFD.bit 0) is set.
29 Host Bus Fatal Error Status (HBFS) — R/WC. Indicates that Intel® Xeon® Processor D-1500
Product Family encountered an error that it cannot recover from due to a bad software pointer. In
PCI, such an indication would be a target or master abort.
28 Host Bus Data Error Status (HBDS) — R/WC. Indicates that Intel® Xeon® Processor D-1500
Product Family encountered a data error (uncorrectable ECC / parity) when reading from or writing to
system memory.
27 Interface Fatal Error Status (IFS) — R/WC. Indicates that Intel® Xeon® Processor D-1500
Product Family encountered an error on the SATA interface which caused the transfer to stop.
26 Interface Non-fatal Error Status (INFS) — R/WC. Indicates that Intel® Xeon® Processor D-1500
Product Family encountered an error on the SATA interface but was able to continue operation.
25 Reserved
24 Overflow Status (OFS) — R/WC. Indicates that Intel® Xeon® Processor D-1500 Product Family
received more bytes from a device than was specified in the PRD table for the command.
23 Incorrect Port Multiplier Status (IPMS) — R/WC. Intel® Xeon® Processor D-1500 Product Family
SATA controller does not support Port Multipliers.
22 PhyRdy Change Status (PRCS) — RO. When set to one, this bit indicates the internal PhyRdy
signal changed state. This bit reflects the state of PxSERR.DIAG.N. Unlike most of the other bits in the
register, this bit is RO and is only cleared when PxSERR.DIAG.N is cleared.
The internal PhyRdy signal also transitions when the port interface enters partial or slumber power
management states. Partial and slumber must be disabled when Surprise Removal Notification is
desired, otherwise the power management state transitions will appear as false insertion and removal
events.
21:8 Reserved
7 Device Interlock Status (DIS) — R/WC. When set, this bit indicates that a platform mechanical
presence switch has been opened or closed, which may lead to a change in the connection state of
the device. This bit is only valid in systems that support an mechanical presence switch (CAP.SIS
[ABAR+00:bit 28] set).
For systems that do not support an mechanical presence switch, this bit will always be 0.