Datasheet

SATA Controller Registers (D31:F2)
Intel® Xeon® Processor D-1500 Product Family 359
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
8.4.2.1 PxCLB—Port [5:0] Command List Base Address Register (D31:F2)
Address Offset: Port 0: ABAR + 100h Attribute: R/W
Port 1: ABAR + 180h
Port 2: ABAR + 200h (if port available; see Section 1.3)
Port 3: ABAR + 280h (if port available; see Section 1.3)
Port 4: ABAR + 300h
Port 5: ABAR + 380h
Default Value: Undefined Size: 32 bits
8.4.2.2 PxCLBU—Port [5:0] Command List Base Address Upper 32-Bits
Register (D31:F2)
Address Offset: Port 0: ABAR + 104h Attribute: R/W
Port 1: ABAR + 184h
Port 2: ABAR + 204h (if port available; see Section 1.3)
Port 3: ABAR + 284h (if port available; see Section 1.3)
Port 4: ABAR + 304h
Port 5: ABAR + 384h
Default Value: Undefined Size: 32 bits
8.4.2.3 PxFB—Port [5:0] FIS Base Address Register (D31:F2)
Address Offset: Port 0: ABAR + 108h Attribute: R/W
Port 1: ABAR + 188h
Port 2: ABAR + 208h (if port available; see Section 1.3)
Port 3: ABAR + 288h (if port available; see Section 1.3)
Port 4: ABAR + 308h
Port 5: ABAR + 388h
Default Value: Undefined Size: 32 bits
Bit Description
31:10 Command List Base Address (CLB) — R/W. Indicates the 32-bit base for the command list for this
port. This base is used when fetching commands to execute. The structure pointed to by this address
range is 1 KB in length. This address must be 1-KB aligned as indicated by bits 31:10 being read/
write.
These bits are not reset on a controller reset.
9:0 Reserved
Bit Description
31:0 Command List Base Address Upper (CLBU) — R/W. Indicates the upper 32-bits for the command
list base address for this port. This base is used when fetching commands to execute.
These bits are not reset on a controller reset.
Bit Description
31:8 FIS Base Address (FB) — R/W. Indicates the 32-bit base for received FISes. The structure pointed
to by this address range is 256 bytes in length. This address must be 256-byte aligned, as indicated
by bits 31:3 being read/write.
These bits are not reset on a controller reset.
7:0 Reserved