Datasheet

SATA Controller Registers (D31:F2)
356 Intel® Xeon® Processor D-1500 Product Family
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
8.4.1.8 CAP2—HBA Capabilities Extended Register
Address Offset: ABAR + 24h–27h Attribute: RO
Default Value: 00000004h Size: 32 bits
Function Level Reset:No
8.4.2 Port Registers (D31:F2)
Ports not available will result in the corresponding Port DMA register space being
reserved. The controller shall ignore writes to the reserved space on write cycles and
shall return 0 on read cycle accesses to the reserved location.
19 SGPIO Enclosure Management Messages (SUPP.SGPIO) — RO.
1 = The SATA controller supports the SGPIO register interface message type.
18 SES-2 Enclosure Management Messages (SUPP.SES2) — RO.
1 = The SATA controller supports the SES-2 message type.
17 SAF-TE Enclosure Management Messages (SUPP.SAFTE) — RO.
1 = The SATA controller supports the SAF-TE message type.
16 LED Message Types (SUPP.LED) — RO.
1 = The SATA controller supports the LED message type.
15:10 Reserved
9 Reset (RST): — R/W.
0 = A write of 0 to this bit by software will have no effect.
1 = When set by software, The SATA controller resets all enclosure management message logic
and takes all appropriate reset actions to ensure messages can be transmitted / received after
the reset. After the SATA controller completes the reset operation, the SATA controller sets the
value to 0.
8 Transmit Message (CTL.TM) — R/W.
0 = A write of 0 to this bit by software will have no effect.
1 = When set by software, The SATA controller transmits the message contained in the message
buffer. When the message is completely sent, the SATA controller sets the value to 0.
Software must not change the contents of the message buffer while CTL.TM is set to 1.
7:1 Reserved
0 Message Received (STS.MR): — RO. Message Received is not supported in Intel® Xeon®
Processor D-1500 Product Family.
Bit Description
Bit Description
31:3 Reserved
2 Automatic Partial to Slumber Transitions (APST)
0= Not supported
1= Supported
1:0 Reserved
Table 8-5. Port [5:0] DMA Register Address Map (Sheet 1 of 3)
ABAR + Offset Mnemonic Register
100h–103h P0CLB Port 0 Command List Base Address
104h–107h P0CLBU Port 0 Command List Base Address Upper 32-Bits
108h–10Bh P0FB Port 0 FIS Base Address
10Ch–10Fh P0FBU Port 0 FIS Base Address Upper 32-Bits
110h–113h P0IS Port 0 Interrupt Status
114h–117h P0IE Port 0 Interrupt Enable
118h–11Bh P0CMD Port 0 Command
11Ch–11Fh — Reserved