Datasheet

SATA Controller Registers (D31:F2)
354 Intel® Xeon® Processor D-1500 Product Family
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
8.4.1.4 PI—Ports Implemented Register (D31:F2)
Address Offset: ABAR + 0Ch–0Fh Attribute: R/WO, RO
Default Value: 00000000h Size: 32 bits
Function Level Reset:No
This register indicates which ports are exposed to Intel® Xeon® Processor D-1500
Product Family. It is loaded by platform BIOS. It indicates which ports that the device
supports are available for software to use. For ports that are not available, software
must not read or write to registers within that port. After BIOS issues initial write to
this register, BIOS is requested to issue two reads to this register. If BIOS accesses any
of the port specific AHCI address range before setting PI bit, BIOS is required to read
the PI register before the initial write to the PI register.
4 Interrupt Pending Status Port[4] (IPS[4]) — R/WC.
0 = No interrupt pending.
1 = Port 4 has an interrupt pending. Software can use this information to determine which ports
require service after an interrupt.
3 Interrupt Pending Status Port[3] (IPS[3]) — R/WC.
0 = No interrupt pending.
1 = Port 3 has an interrupt pending. Software can use this information to determine which ports
require service after an interrupt.
2 Interrupt Pending Status Port[2] (IPS[2]) — R/WC.
0 = No interrupt pending.
1 = Port 2 has an interrupt pending. Software can use this information to determine which ports
require service after an interrupt.
1 Interrupt Pending Status Port[1] (IPS[1]) — R/WC.
0 = No interrupt pending.
1 = Port 1has an interrupt pending. Software can use this information to determine which ports
require service after an interrupt.
0 Interrupt Pending Status Port[0] (IPS[0]) — R/WC.
0 = No interrupt pending.
1 = Port 0 has an interrupt pending. Software can use this information to determine which ports
require service after an interrupt.
Bit Description
Bit Description
31:6 Reserved. Returns 0.
5 Ports Implemented Port 5 (PI5) — R/WO.
0 = The port is not implemented.
1 = The port is implemented.
This bit is read-only 0 if this is a PCIe Port, MAP.SC = 0 or SCC = 01h.
4 Ports Implemented Port 4 (PI4) — R/WO.
0 = The port is not implemented.
1 = The port is implemented.
This bit is read-only 0 if this is a PCIe Port, MAP.SC = 0 or SCC = 01h.
3 Ports Implemented Port 3 (PI3) — R/WO.
0 = The port is not implemented.
1 = The port is implemented.
2 Ports Implemented Port 2 (PI2)— R/WO.
0 = The port is not implemented.
1 = The port is implemented.
1 Ports Implemented Port 1 (PI1) — R/WO.
0 = The port is not implemented.
1 = The port is implemented.
0 Ports Implemented Port 0 (PI0) — R/WO.
0 = The port is not implemented.
1 = The port is implemented.