Datasheet

SATA Controller Registers (D31:F2)
Intel® Xeon® Processor D-1500 Product Family 353
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
8.4.1.2 GHC—Global Intel® Xeon® Processor D-1500 Product Family Control
Register (D31:F2)
Address Offset: ABAR + 04h–07h Attribute: R/W, RO
Default Value: 00000000h Size: 32 bits
8.4.1.3 IS—Interrupt Status Register (D31:F2)
Address Offset: ABAR + 08h–0Bh Attribute: R/WC
Default Value: 00000000h Size: 32 bits
This register indicates which of the ports within the controller have an interrupt pending
and require service.
Bit Description
31 AHCI Enable (AE) — R/W. When set, this bit indicates that an AHCI driver is loaded and the
controller will be talked to using AHCI mechanisms. This can be used by an Intel® Xeon® Processor
D-1500 Product Family that supports both legacy mechanisms (such as SFF-8038i) and AHCI to
know when the controller will not be talked to as legacy.
0 = Software will communicate with Intel® Xeon® Processor D-1500 Product Family using legacy
mechanisms.
1 = Software will communicate with Intel® Xeon® Processor D-1500 Product Family using AHCI.
Intel® Xeon® Processor D-1500 Product Family will not have to allow command processing
using both AHCI and legacy mechanisms.
Software shall set this bit to 1 before accessing other AHCI registers.
30:3 Reserved
2 MSI Revert to Single Message (MRSM) — RO: When set to 1 by hardware, this bit indicates that
the host controller requested more than one MSI vector but has reverted to using the first vector
only. When this bit is cleared to 0, the controller has not reverted to single MSI mode (that is,
hardware is already in single MSI mode, software has allocated the number of messages requested,
or hardware is sharing interrupt vectors if MC.MME < MC.MMC).
"MC.MSIE = 1 (MSI is enabled)
"MC.MMC > 0 (multiple messages requested)
"MC.MME > 0 (more than one message allocated)
"MC.MME!= MC.MMC (messages allocated not equal to number requested)
When this bit is set to 1, single MSI mode operation is in use and software is responsible for clearing
bits in the IS register to clear interrupts.
This bit shall be cleared to 0 by hardware when any of the four conditions stated is false. This bit is
also cleared to 0 when MC.MSIE = 1 and MC.MME = 0h. In this case, the hardware has been
programmed to use single MSI mode, and is not “reverting” to that mode.
For Intel® Xeon® Processor D-1500 Product Family, the controller shall always revert to single MSI
mode when the number of vectors allocated by the host is less than the number requested. This bit
is ignored when GHC.HR = 1.
1 Interrupt Enable (IE) — R/W. This global bit enables interrupts from Intel® Xeon® Processor D-
1500 Product Family.
0 = All interrupt sources from all ports are disabled.
1 = Interrupts are allowed from the AHCI controller.
0 Controller Reset (HR) — R/W. Resets Intel® Xeon® Processor D-1500 Product Family AHCI
controller.
0 = No effect
1 = When set by software, this bit causes an internal reset of Intel® Xeon® Processor D-1500
Product Family AHCI controller. All state machines that relate to data transfers and queuing
return to an idle condition, and all ports are re-initialized using COMRESET.
Note: For further details, consult Section 10.4.3 of the Serial ATA Advanced Host Controller
Interface Specification, Revision 1.3.
Bit Description
31:6 Reserved. Returns 0.
5 Interrupt Pending Status Port[5] (IPS[5]) — R/WC.
0 = No interrupt pending.
1 = Port 5 has an interrupt pending. Software can use this information to determine which ports
require service after an interrupt.