Datasheet
SATA Controller Registers (D31:F2)
Intel® Xeon® Processor D-1500 Product Family 351
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
The registers are broken into two sections – generic host control and port control. The
port control registers are the same for all ports, and there are as many registers banks
as there are ports.
8.4.1 AHCI Generic Host Control Registers (D31:F2)
8.4.1.1 CAP—Host Capabilities Register (D31:F2)
Address Offset: ABAR + 00h–03h Attribute: R/WO, RO
Default Value: FF22FFC2h Size: 32 bits
Function Level Reset:No
All bits in this register that are R/WO are reset only by PLTRST#.
Table 8-3. AHCI Register Address Map
ABAR + Offset Mnemonic Register
00–1Fh GHC Generic Host Control
20h–FFh — Reserved
100h–17Fh P0PCR Port 0 port control registers
180h–1FFh P1PCR Port 1 port control registers
200h–27Fh P2PCR Port 2 port control registers
280h–2FFh P3PCR Port 3 port control registers
300h–37Fh P4PCR Port 4 port control registers
380h–3FFh P5PCR Port 5 port control registers
Table 8-4. Generic Host Controller Register Address Map
ABAR +
Offset
Mnemonic Register Default Attribute
00h–03h CAP Host Capabilities FF22FFC2h R/WO, RO
04h–07h GHC Global Intel® Xeon® Processor D-1500
Product Family Control
00000000h R/W, RO
08h–0Bh IS Interrupt Status 00000000h R/WC
0Ch–0Fh PI Ports Implemented 00000000h R/WO, RO
10h–13h VS AHCI Version 00010300h RO
1Ch–1Fh EM_LOC Enclosure Management Location 01600002h RO
20h–23h EM_CTRL Enclosure Management Control 07010000h R/W, R/WO,
RO
24h–27h CAP2 HBA Capabilities Extended 00000004h RO
Bit Description
31 Supports 64-bit Addressing (S64A) — RO. Indicates that the SATA controller can access 64-
bit data structures. The 32-bit upper bits of the port DMA Descriptor, the PRD Base, and each
PRD entry are read/write.
30 Supports Command Queue Acceleration (SCQA) — R/WO. When set to 1, indicates that the
SATA controller supports SATA command queuing using the DMA Setup FIS. Intel® Xeon®
Processor D-1500 Product Family handles DMA Setup FISes natively, and can handle auto-
activate optimization through that FIS.
29 Supports SNotification Register (SSNTF) — R/WO. Intel® Xeon® Processor D-1500
Product Family SATA Controller does not support the SNotification register. BIOS must write a 0
to this field.