Datasheet

SATA Controller Registers (D31:F2)
350 Intel® Xeon® Processor D-1500 Product Family
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
8.4 AHCI Registers (D31:F2)
Note: These registers are AHCI-specific and available when Intel® Xeon® Processor D-1500
Product Family is properly configured. The Serial ATA Status, Control, and Error
registers are special exceptions and may be accessed on all Intel® Xeon® Processor D-
1500 Product Family components if properly configured; see Section 8.3 for details.
The memory mapped registers within the SATA controller exist in non-cacheable
memory space. Additionally, locked accesses are not supported. If software attempts to
perform locked transactions to the registers, indeterminate results may occur. Register
accesses shall have a maximum size of 64-bits; 64-bit access must not cross an 8-byte
alignment boundary. All memory registers are reset by Function Level Reset unless
specified otherwise.
25 Unrecognized FIS Type (F): Indicates that one or more FISs were received by the Transport layer
with good CRC, but had a type field that was not recognized.
24 Transport state transition error (T): Indicates that an error has occurred in the transition from
one state to another within the Transport layer since the last time this bit was cleared.
23 Link Sequence Error (S): Indicates that one or more Link state machine error conditions was
encountered. The Link Layer state machine defines the conditions under which the link layer detects
an erroneous transition.
22 Handshake (H). Indicates that one or more R_ERR handshake response was received in response
to frame transmission. Such errors may be the result of a CRC error detected by the recipient, a
disparity or 8b/10b decoding error, or other error condition leading to a negative handshake on a
transmitted frame.
21 CRC Error (C). Indicates that one or more CRC errors occurred with the Link Layer.
20 Disparity Error (D). This field is not used by AHCI.
19 10b to 8b Decode Error (B). Indicates that one or more 10b to 8b decoding errors occurred.
18 Comm Wake (W). Indicates that a Comm Wake signal was detected by the Phy.
17 Phy Internal Error (I). Indicates that the Phy detected some internal error.
16 PhyRdy Change (N): When set to 1, this bit indicates that the internal PhyRdy signal changed state
since the last time this bit was cleared. In Intel® Xeon® Processor D-1500 Product Family, this bit
will be set when PhyRdy changes from a 0 -> 1 or a 1 -> 0. The state of this bit is then reflected in
the PxIS.PRCS interrupt status bit and an interrupt will be generated if enabled. Software clears this
bit by writing a 1 to it.
15:12 Reserved
11 Internal Error (E). The SATA controller failed due to a master or target abort when attempting to
access system memory.
10 Protocol Error (P). A violation of the Serial ATA protocol was detected.
Note: Intel® Xeon® Processor D-1500 Product Family does not set this bit for all protocol
violations that may occur on the SATA link.
9 Persistent Communication or Data Integrity Error (C). A communication error that was not
recovered occurred that is expected to be persistent. Persistent communications errors may arise
from faulty interconnect with the device, from a device that has been removed or has failed, or a
number of other causes.
8 Transient Data Integrity Error (T): A data integrity error occurred that was not recovered by the
interface.
7:2 Reserved
1 Recovered Communications Error (M). Communications between the device and host was
temporarily lost but was re-established. This can arise from a device temporarily being removed,
from a temporary loss of Phy synchronization, or from other causes and may be derived from the
PhyNRdy signal between the Phy and Link layers.
0 Recovered Data Integrity Error (I). A data integrity error occurred that was recovered by the
interface through a retry operation or other recovery action.
Bit Description