Datasheet

SATA Controller Registers (D31:F2)
346 Intel® Xeon® Processor D-1500 Product Family
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
8.2.3 BMID[P,S]—Bus Master IDE Descriptor Table Pointer
Register (D31:F2)
Address Offset: Primary: BAR + 04h–07h Attribute: R/W
Secondary: BAR + 0Ch–0Fh
Default Value: All bits undefined Size: 32 bits
8.2.4 AIR—AHCI Index Register (D31:F2)
Address Offset: Primary: BAR + 10h Attribute: R/W
Default Value: 00000000h Size: 32 bits
This register is available only when SCC is not 01h.
8.2.5 AIDR—AHCI Index Data Register (D31:F2)
Address Offset: Primary: BAR + 14h Attribute: R/W
Default Value: All bits undefined Size: 32 bits
This register is available only when SCC is not 01h.
1 Error — R/WC.
0 = Software clears this bit by writing a 1 to it.
1 = This bit is set when the controller encounters a target abort or master abort when transferring
data on PCI.
0 Bus Master IDE Active (ACT) — RO.
0 = This bit is cleared by Intel® Xeon® Processor D-1500 Product Family when the last transfer for
a region is performed, where EOT for that region is set in the region descriptor. It is also cleared
by Intel® Xeon® Processor D-1500 Product Family when the Start Bus Master bit
(D31:F2:BAR+ 00h, bit 0) is cleared in the Command register. When this bit is read as a 0, all
data transferred from the drive during the previous bus master command is visible in system
memory, unless the bus master command was aborted.
1 = Set by Intel® Xeon® Processor D-1500 Product Family when the Start bit is written to the
Command register.
Bit Description
Bit Description
31:2 Address of Descriptor Table (ADDR) — R/W. The bits in this field correspond to bits [31:2] of the
memory location of the Physical Region Descriptor (PRD). The Descriptor Table must be DWord-
aligned. The Descriptor Table must not cross a 64-K boundary in memory.
1:0 Reserved
Bit Description
31:11 Reserved
10:2 Index (INDEX)— R/W. This Index register is used to select the DWord offset of the Memory
Mapped AHCI register to be accessed. A DWord, Word or Byte access is specified by the active byte
enables of the I/O access to the Data register.
1:0 Reserved
Bit Description
31:0 Data (DATA)— R/W: This Data register is a “window” through which data is read or written to the
AHCI memory mapped registers. A read or write to this Data register triggers a corresponding read
or write to the memory mapped register pointed to by the Index register. The Index register must be
setup prior to the read or write to this Data register.
A physical register is not actually implemented as the data is actually stored in the memory mapped
registers.
Since this is not a physical register, the “default” value is the same as the default value of the
register pointed to by Index.