Datasheet

SATA Controller Registers (D31:F2)
344 Intel® Xeon® Processor D-1500 Product Family
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
8.1.47 BFTD1—BIST FIS Transmit Data1 Register (SATA–D31:F2)
Address Offset: E4h–E7h Attribute: R/W
Default Value: 00000000h Size: 32 bits
8.1.48 BFTD2—BIST FIS Transmit Data2 Register (SATA–D31:F2)
Address Offset: E8h–EBh Attribute: R/W
Default Value: 00000000h Size: 32 bits
8.2 Bus Master IDE I/O Registers (D31:F2)
The bus master IDE function uses 16 bytes of I/O space, allocated using the BAR
register, located in D31:F2 Configuration space, offset 20h. All bus master IDE I/O
space registers can be accessed as byte, word, or DWord quantities. Reading reserved
bits returns an indeterminate, inconsistent value, and writes to reserved bits have no
affect (but should not be attempted). These registers are only used for legacy
operation. Software must not use these registers when running AHCI. All I/O registers
are reset by Function Level Reset. The register address I/O map is shown in Tabl e 8- 2 .
Bits Description
31:0 BIST FIS Transmit Data 1 — R/W. The data programmed into this register will form the contents
of the second DWord of any BIST FIS initiated by Intel® Xeon® Processor D-1500 Product Family.
This register is not port specific—its contents will be used for BIST FIS initiated on any port. Although
the 2nd and 3rd DWs of the BIST FIS are only meaningful when the “T” bit of the BIST FIS is set to
indicate “Far-End Transmit mode”, this register’s contents will be transmitted as the BIST FIS 2nd
DW regardless of whether or not the “T” bit is indicated in the BFCS register (D31:F2:E0h).
Bits Description
31:0 BIST FIS Transmit Data 2 — R/W. The data programmed into this register will form the contents
of the third DWord of any BIST FIS initiated by Intel® Xeon® Processor D-1500 Product Family. This
register is not port specific—its contents will be used for BIST FIS initiated on any port. Although the
2nd and 3rd DWs of the BIST FIS are only meaningful when the “T” bit of the BIST FIS is set to
indicate “Far-End Transmit mode”, this register’s contents will be transmitted as the BIST FIS 3rd DW
regardless of whether or not the “T” bit is indicated in the BFCS register (D31:F2:E0h).
Table 8-2. Bus Master IDE I/O Register Address Map
BAR+
Offset
Mnemonic Register Default Attribute
00h BMICP Command Register Primary 00h R/W
01h — Reserved — RO
02h BMISP Bus Master IDE Status Register Primary 00h R/W, R/WC, RO
03h — Reserved — RO
04h–07h BMIDP Bus Master IDE Descriptor Table Pointer Primary xxxxxxxxh R/W
08h BMICS Command Register Secondary 00h R/W
09h — Reserved — RO
0Ah BMISS Bus Master IDE Status Register Secondary 00h R/W, R/WC, RO
0Bh — Reserved — RO
0Ch–0Fh BMIDS Bus Master IDE Descriptor Table Pointer
Secondary
xxxxxxxxh R/W
10h AIR AHCI Index Register 00000000h R/W, RO
14h AIDR AHCI Index Data Register xxxxxxxxh R/W