Datasheet

SATA Controller Registers (D31:F2)
Intel® Xeon® Processor D-1500 Product Family 343
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
12 Port 2 BIST FIS Initiate (P2BFI) — R/W. When a rising edge is detected on this bit field,
Intel® Xeon® Processor D-1500 Product Family initiates a BIST FIS to the device on Port 2, using
the parameters specified in this register and the data specified in BFTD1 and BFTD2. The BIST FIS
will only be initiated if a device on Port 2 is present and ready (not partial/slumber state). After a
BIST FIS is successfully completed, software must disable and re-enable the port using the PxE
bits at offset 92h prior to attempting additional BIST FISes or to return Intel® Xeon® Processor
D-1500 Product Family to a normal operational mode. If the BIST FIS fails to complete, as
indicated by the BFF bit in the register, then software can clear then set the P2BFI bit to initiate
another BIST FIS. This can be retried until the BIST FIS eventually completes successfully.
11 BIST FIS Successful (BFS) — R/WC.
0 = Software clears this bit by writing a 1 to it.
1 = This bit is set any time a BIST FIS transmitted by Intel® Xeon® Processor D-1500 Product
Family receives an R_OK completion status from the device.
Note: This bit must be cleared by software prior to initiating a BIST FIS.
10 BIST FIS Failed (BFF) — R/WC.
0 = Software clears this bit by writing a 1 to it.
1 = This bit is set any time a BIST FIS transmitted by Intel® Xeon® Processor D-1500 Product
Family receives an R_ERR completion status from the device.
Note: This bit must be cleared by software prior to initiating a BIST FIS.
9 Port 1 BIST FIS Initiate (P1BFI) — R/W. When a rising edge is detected on this bit field,
Intel® Xeon® Processor D-1500 Product Family initiates a BIST FIS to the device on Port 1, using
the parameters specified in this register and the data specified in BFTD1 and BFTD2. The BIST FIS
will only be initiated if a device on Port 1 is present and ready (not partial/slumber state). After a
BIST FIS is successfully completed, software must disable and re-enable the port using the PxE
bits at offset 92h prior to attempting additional BIST FISes or to return Intel® Xeon® Processor
D-1500 Product Family to a normal operational mode. If the BIST FIS fails to complete, as
indicated by the BFF bit in the register, then software can clear then set the P1BFI bit to initiate
another BIST FIS. This can be retried until the BIST FIS eventually completes successfully.
8 Port 0 BIST FIS Initiate (P0BFI) — R/W. When a rising edge is detected on this bit field,
Intel® Xeon® Processor D-1500 Product Family initiates a BIST FIS to the device on Port 0, using
the parameters specified in this register and the data specified in BFTD1 and BFTD2. The BIST FIS
will only be initiated if a device on Port 0 is present and ready (not partial/slumber state). After a
BIST FIS is successfully completed, software must disable and re-enable the port using the PxE
bits at offset 92h prior to attempting additional BIST FISes or to return Intel® Xeon® Processor
D-1500 Product Family to a normal operational mode. If the BIST FIS fails to complete, as
indicated by the BFF bit in the register, then software can clear then set the P0BFI bit to initiate
another BIST FIS. This can be retried until the BIST FIS eventually completes successfully.
7:2 BIST FIS Parameters (BFP) — R/W. These 6 bits form the contents of the upper 6 bits of the
BIST FIS Pattern Definition in any BIST FIS transmitted by Intel® Xeon® Processor D-1500
Product Family. This field is not port specific — its contents will be used for any BIST FIS initiated
on port 0, port 1, port 2, or port 3. The specific bit definitions are:
Bit 7: T – Far End Transmit mode
Bit 6: A – Align Bypass mode
Bit 5: S – Bypass Scrambling
Bit 4: L – Far End Retimed Loopback
Bit 3: F – Far End Analog Loopback
Bit 2: P – Primitive bit for use with Transmit mode
1:0 Reserved
Bits Description