Datasheet

SATA Controller Registers (D31:F2)
342 Intel® Xeon® Processor D-1500 Product Family
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
8.1.44 ATS—APM Trapping Status Register (SATA–D31:F2)
Address Offset: C4h Attribute: R/WC
Default Value: 00h Size: 8 bits
Function Level Reset:No
.
8.1.45 SP—Scratch Pad Register (SATA–D31:F2)
Address Offset: D0h Attribute: R/W
Default Value: 00000000h Size: 32 bits
.
8.1.46 BFCS—BIST FIS Control/Status Register (SATA–D31:F2)
Address Offset: E0h–E3h Attribute: R/W, R/WC
Default Value: 00000000h Size: 32 bits
Bit Description
7:4 Reserved
3 Secondary Slave Trap (SST) — R/WC. Indicates that a trap occurred to the secondary slave
device.
2 Secondary Master Trap (SPT) — R/WC. Indicates that a trap occurred to the secondary master
device.
1 Primary Slave Trap (PST) — R/WC. Indicates that a trap occurred to the primary slave device.
0 Primary Master Trap (PMT) — R/WC. Indicates that a trap occurred to the primary master device.
Bit Description
31:0 Data (DT) — R/W. This is a read/write register that is available for software to use. No hardware
action is taken on this register.
Bits Description
31:16 Reserved
15 Port 5 BIST FIS Initiate (P5BFI) — R/W. When a rising edge is detected on this bit field,
Intel® Xeon® Processor D-1500 Product Family initiates a BIST FIS to the device on Port 5, using
the parameters specified in this register and the data specified in BFTD1 and BFTD2. The BIST FIS
will only be initiated if a device on Port 5 is present and ready (not partial/slumber state). After a
BIST FIS is successfully completed, software must disable and re-enable the port using the PxE
bits at offset 92h prior to attempting additional BIST FISs or to return Intel® Xeon® Processor D-
1500 Product Family to a normal operational mode. If the BIST FIS fails to complete, as indicated
by the BFF bit in the register, then software can clear then set the P5BFI bit to initiate another
BIST FIS. This can be retried until the BIST FIS eventually completes successfully.
14 Port 4 BIST FIS Initiate (P4BFI) — R/W. When a rising edge is detected on this bit field,
Intel® Xeon® Processor D-1500 Product Family initiates a BIST FIS to the device on Port 4, using
the parameters specified in this register and the data specified in BFTD1 and BFTD2. The BIST FIS
will only be initiated if a device on Port 4 is present and ready (not partial/slumber state). After a
BIST FIS is successfully completed, software must disable and re-enable the port using the PxE
bits at offset 92h prior to attempting additional BIST FISs or to return Intel® Xeon® Processor D-
1500 Product Family to a normal operational mode. If the BIST FIS fails to complete, as indicated
by the BFF bit in the register, then software can clear then set the P4BFI bit to initiate another
BIST FIS. This can be retried until the BIST FIS eventually completes successfully.
13 Port 3 BIST FIS Initiate (P3BFI) — R/W. When a rising edge is detected on this bit field,
Intel® Xeon® Processor D-1500 Product Family initiates a BIST FIS to the device on Port 3, using
the parameters specified in this register and the data specified in BFTD1 and BFTD2. The BIST FIS
will only be initiated if a device on Port 3 is present and ready (not partial/slumber state). After a
BIST FIS is successfully completed, software must disable and re-enable the port using the PxE
bits at offset 92h prior to attempting additional BIST FISs or to return Intel® Xeon® Processor D-
1500 Product Family to a normal operational mode. If the BIST FIS fails to complete, as indicated
by the BFF bit in the register, then software can clear then set the P3BFI bit to initiate another
BIST FIS. This can be retried until the BIST FIS eventually completes successfully.