Datasheet

SATA Controller Registers (D31:F2)
Intel® Xeon® Processor D-1500 Product Family 341
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
8.1.41 FLRCLV—FLR Capability Length and Version Register
(SATA–D31:F2)
Address Offset: B2–B3h Attribute: RO, R/WO
Default Value: xx06h Size: 16 bits
Function Level Reset:No (Bit 9:8 Only when FLRCSSEL = 0)
When FLRCSSEL (RCBA+3410h:bit 12) = 1, this register is RO:
8.1.42 FLRC—FLR Control Register (SATA–D31:F2)
Address Offset: B4–B5h Attribute: RO, R/W
Default Value: 0000h Size: 16 bits
When FLRCSSEL (RCBA+3410h:bit 12) = 1, this register is RO.
8.1.43 ATC—APM Trapping Control Register (SATA–D31:F2)
Address Offset: C0h Attribute: R/W
Default Value: 00h Size: 8 bits
Function Level Reset:No
.
Bit Description
15:10 Reserved
9 FLR Capability — R/WO.
1 = Support for Function Level reset.
This bit is not reset by the Function Level Reset.
8 TXP Capability — R/WO.
1 = Support for Transactions Pending (TXP) bit. TXP must be supported if FLR is supported.
7:0 Vendor-Specific Capability ID — RO. This field indicates the number of bytes of this Vendor
Specific capability as required by the PCI specification. It has the value of 06h for the FLR capability.
Bit Description
15:9 Reserved
8 Transactions Pending (TXP) — RO.
0 = Controller has received all non-posted requests.
1 = Controller has issued non-posted requests which has not been completed.
7:1 Reserved
0 Initiate FLR — R/W. Used to initiate FLR transition. A write of 1 indicates FLR transition. Since
hardware must not respond to any cycles till FLR completion the value read by software from this bit
is 0.
Bit Description
7:4 Reserved
3 Secondary Slave Trap (SST) — R/W. Enables trapping and SMI# assertion on legacy I/O accesses
to 170h–177h and 376h. The active device on the secondary interface must be device 1 for the trap
and/or SMI# to occur.
2 Secondary Master Trap (SPT) — R/W. Enables trapping and SMI# assertion on legacy I/O
accesses to 170h-177h and 376h. The active device on the secondary interface must be device 0 for
the trap and/or SMI# to occur.
1 Primary Slave Trap (PST) — R/W. Enables trapping and SMI# assertion on legacy I/O accesses to
1F0h–1F7h and 3F6h. The active device on the primary interface must be device 1 for the trap and/
or SMI# to occur.
0 Primary Master Trap (PMT) — R/W. Enables trapping and SMI# assertion on legacy I/O accesses
to 1F0h–1F7h and 3F6h. The active device on the primary interface must be device 0 for the trap
and/or SMI# to occur.