Datasheet
SATA Controller Registers (D31:F2)
340 Intel® Xeon® Processor D-1500 Product Family
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
8.1.39 SATACR1—SATA Capability Register 1 (SATA–D31:F2)
Address Offset: ACh–AFh Attribute: RO
Default Value: 00000048h Size: 32 bits
Note: When SCC is 01h, this register is read-only 0.
8.1.40 FLRCID—FLR Capability Identification Register (SATA–
D31:F2)
Address Offset: B0–B1h Attribute: RO
Default Value: 0009h Size: 16 bits
19:16 Minor Revision (MINREV) — RO. Minor revision number of the SATA Capability Pointer
implemented.
15:8 Next Capability Pointer (NEXT) — R/WO. Points to the next capability structure.
These bits are not reset by Function Level Reset.
7:0 Capability ID (CAP)— RW. The value 00h indicates the final item in the SATA Capability List.
Note: Refer to the SGC.REGLOCK description in order to lock the register to become RO.
Bit Description
Bit Description
31:16 Reserved
15:4 BAR Offset (BAROFST) — RO. Indicates the offset into the BAR where the Index/Data pair are
located (in DWord granularity). The Index and Data I/O registers are located at offset 10h within the
I/O space defined by LBAR. A value of 004h indicates offset 10h.
000h = 0h offset
001h = 4h offset
002h = 8h offset
003h = Bh offset
004h = 10h offset
...
FFFh = 3FFFh offset (max 16KB)
3:0 BAR Location (BARLOC) — RO. Indicates the absolute PCI Configuration Register address of the
BAR containing the Index/Data pair (in DWord granularity). The Index and Data I/O registers reside
within the space defined by LBAR in the SATA controller. A value of 8h indicates offset 20h, which is
LBAR.
0000 – 0011b = reserved
0100b = 10h => BAR0
0101b = 14h => BAR1
0110b = 18h => BAR2
0111b = 1Ch => BAR3
1000b = 20h => LBAR
1001b = 24h => BAR5
1010–1110b = Reserved
1111b = Index/Data pair in PCI Configuration space. This is not supported in Intel® Xeon®
Processor D-1500 Product Family.
Bit Description
15:8 Next Capability Pointer — RO. 00h indicates the final item in the capability list.
7:0 Capability ID — RO. The value of this field depends on the FLRCSSEL (RCBA+3410h:bit 12) bit.
FLRCSSEL (RCBA+3410h:bit 12)
Value
Capability ID Register
Value
0b 13h
1b 00h (Vendor Specific)