Datasheet

SATA Controller Registers (D31:F2)
Intel® Xeon® Processor D-1500 Product Family 339
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
8.1.37 SGC—SATA General Configuration Register
Address Offset: 9Ch–9Fh Attribute: R/W, R/WO
Default Value: 00000000h Size: 32 bits
Function Level Reset: No
8.1.37.1
8.1.38 SATACR0—SATA Capability Register 0 (SATA–D31:F2)
Address Offset: A8h–ABh Attribute: RO, R/WO
Default Value: 0010B012h Size: 32 bits
Function Level Reset: No (Bits 15:8 only)
Note: This register is read-only 0 when SCC is 01h.
29:24 Port Clock Disable (PCD) — R/W.
0 = All clocks to the associated port logic will operate normally.
1 = The backbone clock driven to the associated port logic is gated and will not toggle.
Bit 29: Port 5
Bit 28: Port 4
Bit 27: Port 3
BIt 26: Port 2
Bit 25: Port 1
Bit 24: Port 0
If a port is not available, software shall set the corresponding bit to 1. Software can also set the
corresponding bits to 1 on ports that are disabled.
Software cannot set the PCD [port x]=1 if the corresponding PCS.PxE=1 in either Dev31Func2 or
Dev31Func5 (dual controller IDE mode) or AHCI GHC.PI[x] = “1”.
23:0 Reserved
Bit Description
Bit Description
31 Register Lock (REGLOCK) — R/WO.
0 = Will not lock CAP.CAP_PTR, PID.NEXT, MSICI.NEXT, or SATACR0.NEXT
1 = Setting this bit will lock CAP.CAP_PTR, PID.NEXT, MSICI.NEXT, and SATACR0.NEXT. Once
locked these register bits will become RO. BIOS is requested to program this field prior to
IOS handoff.
This bit is not reset by a Function Level Reset.
30:8 Reserved
7 Alternate ID Enable (AIE) — R/WO. BIOS must write to this bit field.
6 Alternate ID Select (AIES) — R/WO. BIOS must write to this bit field.
5 Reserved - BIOS may write to this field.
4:1 Reserved
0 SATA 4-port All Master Configuration Indicator (SATA4PMIND) — RO.
0 = Normal configuration.
1 = Two IDE Controllers are implemented, each supporting two ports for a Primary Master and
a Secondary Master.
Note: BIOS must also make sure that corresponding port clocks are gated (using SCLKCG
configuration register).
Bit Description
31:24 Reserved
23:20 Major Revision (MAJREV) — RO. Major revision number of the SATA Capability Pointer
implemented.