Datasheet

SATA Controller Registers (D31:F2)
338 Intel® Xeon® Processor D-1500 Product Family
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
8.1.36 SCLKCG—SATA Clock Gating Control Register
Address Offset: 94h–97h Attribute: R/W
Default Value: 00000000h Size: 32 bits
5 Port 5 Enabled (P5E) — R/W / RO.
0 = Disabled. The port is in the ‘off’ state and cannot detect any devices.
1 = Enabled. The port can transition between the on, partial, and slumber states and can detect
devices.
Notes:
1. This bit takes precedence over P5CMD.SUD (offset ABAR+398h:bit 1)
2. If MAP.SC is 0, SCC is 01h, MAP.SPD[5] is 1h,or set to a PCIe* Port then this bit will be read
only 0.
4 Port 4 Enabled (P4E) — R/W / RO.
0 = Disabled. The port is in the ‘off’ state and cannot detect any devices.
1 = Enabled. The port can transition between the on, partial, and slumber states and can detect
devices.
Note:
1. This bit takes precedence over P4CMD.SUD (offset ABAR+318h:bit 1)
2. If MAP.SC is 0, SCC is 01h, MAP.SPD[4] is 1h,or set to a PCIe Port then this bit will be read
only 0.
3 Port 3 Enabled (P3E) — R/W / RO.
0 = Disabled. The port is in the ‘off’ state and cannot detect any devices.
1 = Enabled. The port can transition between the on, partial, and slumber states and can detect
devices.
Notes:
1. This bit takes precedence over P3CMD.SUD (offset ABAR+298h:bit 1). When MAP.SPD[3] is
1 this is reserved and is read-only 0.
2 Port 2 Enabled (P2E) — R/W / RO.
0 = Disabled. The port is in the ‘off’ state and cannot detect any devices.
1 = Enabled. The port can transition between the on, partial, and slumber states and can detect
devices.
Notes:
1. This bit takes precedence over P2CMD.SUD (offset ABAR+218h:bit 1). When MAP.SPD[2] is
1 this is reserved and is read-only 0.
1 Port 1 Enabled (P1E) — R/W / RO.
0 = Disabled. The port is in the ‘off’ state and cannot detect any devices.
1 = Enabled. The port can transition between the on, partial, and slumber states and can detect
devices.
Note: This bit takes precedence over P1CMD.SUD (offset ABAR+198h:bit 1). When MAP.SPD[1]
is 1 this is reserved and is read-only 0.
0 Port 0 Enabled (P0E) — R/W / RO.
0 = Disabled. The port is in the ‘off’ state and cannot detect any devices.
1 = Enabled. The port can transition between the on, partial, and slumber states and can detect
devices.
Note: This bit takes precedence over P0CMD.SUD (offset ABAR+118h:bit 1). When MAP.SPD[0]
is 1 this is reserved and is read-only 0.
Bits Description
Bit Description
31:30 Reserved