Datasheet

SATA Controller Registers (D31:F2)
334 Intel® Xeon® Processor D-1500 Product Family
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
8.1.30 MSICI—Message Signaled Interrupt Capability
Identification Register (SATA–D31:F2)
Address Offset: 80h–81h Attribute: RO
Default Value: 7005h Size: 16 bits
Note: There is no support for MSI when the software is operating in legacy (IDE) mode when
AHCI is not enabled. Prior to switching from AHCI to IDE mode, software must make
sure that MSI is disabled.
8.1.31 MSIMC—Message Signaled Interrupt Message Control
Register (SATA–D31:F2)
Address Offset: 82h–83h Attribute: R/W, RO
Default Value: 0000h Size: 16 bits
Note: There is no support for MSI when the software is operating in legacy (IDE) mode when
AHCI is not enabled. Prior to switching from AHCI to IDE mode, software must make
sure that MSI is disabled.
8 PME Enable (PMEE) — R/W. When set, the SATA controller asserts PME# when exiting D3
HOT
on a
wake event.
Note: When SCCSCC = 01h, hardware will automatically change the attribute of this bit to RO 0.
Software is advised to clear PMEE and PMES together prior to changing SCC thru MAP.SMS.
This bit is not reset by Function Level Reset.
7:4 Reserved
3 No Soft Reset (NSFRST) — RO. These bits are used to indicate whether devices transitioning from
D3
HOT
state to D0 state will perform an internal reset.
0 = Device transitioning from D3
HOT
state to D0 state perform an internal reset.
1 = Device transitioning from D3
HOT
state to D0 state do not perform an internal reset.
Configuration content is preserved. Upon transition from the D3
HOT
state to D0 state initialized state,
no additional operating system intervention is required to preserve configuration context beyond
writing to the PowerState bits.
Regardless of this bit, the controller transition from D3
HOT
state to D0 state by a system or bus
segment reset will return to the state D0 uninitialized with only PME context preserved if PME is
supported and enabled.
2Reserved
1:0 Power State (PS) — R/W. These bits are used both to determine the current power state of the
SATA controller and to set a new power state.
00 = D0 state
11 = D3
HOT
state
When in the D3
HOT
state, the controller’s configuration space is available; however, the I/O and
memory spaces are not. Additionally, interrupts are blocked.
Bits Description
Bits Description
15:8 Next Pointer (NEXT) — R/W. Indicates the next item in the list is the PCI power management
pointer.
BIOS may program this field to A8h indicating that the next item is Serial ATA Capability Structure.
Note: Refer to the SGC.REGLOCK description in order to lock the register to become RO.
This bit is not reset by a Function Level Reset
7:0 Capability ID (CID) — RO. Capabilities ID indicates MSI.