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SATA Controller Registers (D31:F2)

Intel® Xeon® Processor D-1500 Product Family 333

Datasheet - Volume 1 of 4: Integrated Platform Controller Hub

March 2015

8.1.27 PID—PCI Power Management Capability Identification

Address Offset: 70h–71h Attribute: RO

Default Value: See Register Description Size: 16 bits

8.1.28 PC—PCI Power Management Capabilities Register (SATA–

D31:F2)

Address Offset: 72h–73h Attribute: RO

Default Value: See Register Description Size: 16 bits

8.1.29 PMCS—PCI Power Management Control and Status

Address Offset: 74h–75h Attribute: R/W, R/WC

Default Value: 0008h Size: 16 bits

Function Level Reset: No (Bits 8 and 15)

Bits Description

15:8 Next Capability (NEXT) — R/W. A8h is the location of the Serial ATA capability structure. A8h is

the recommended setting for non-IDE mode.

If the controller is to operate in IDE mode, BIOS is requested to program this field to 00h.

Note: Refer to the SGC.REGLOCK description in order to lock the register to become RO.

7:0 Capability ID (CID) — RO. Hardwired to 01h. Indicates that this pointer is a PCI power

management.

Bits Description

15:11 PME Support (PME_SUP) — RO.

00000 = If SCC = 01h, indicates no PME support in IDE mode.

01000 = If SCC is not 01h, in a non-IDE mode, indicates PME# can be generated from the D3

HOT

state in the SATA host controller.

10 D2 Support (D2_SUP) — RO. Hardwired to 0. The D2 state is not supported

9 D1 Support (D1_SUP) — RO. Hardwired to 0. The D1 state is not supported

8:6 Auxiliary Current (AUX_CUR) — RO. PME# from D3COLD state is not supported, therefore this

field is 000b.

5 Device Specific Initialization (DSI) — RO. Hardwired to 0 to indicate that no device-specific

initialization is required.

4Reserved

3 PME Clock (PME_CLK) — RO. Hardwired to 0 to indicate that PCI clock is not required to generate

PME#.

2:0 Version (VER) — RO. Hardwired to 011 to indicates support for Revision 1.2 of the PCI Power

Management Specification.

Bits Description

15 PME Status (PMES) — R/WC. Bit is set when a PME event is to be requested, and if this bit and

PMEE is set, a PME# will be generated from the SATA controller

Note: When SCC = 01h, hardware will automatically change the attribute of this bit to RO 0.

Software is advised to clear PMEE and PMES together prior to changing SCC thru MAP.SMS.

This bit is not reset by Function Level Reset.

14:9 Reserved