Datasheet

SATA Controller Registers (D31:F2)
332 Intel® Xeon® Processor D-1500 Product Family
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
8.1.24 SDMA_CNT—Synchronous DMA Control Register (SATA–
D31:F2)
Address Offset: 48h Attribute: R/W
Default Value: 00h Size: 8 bits
Note: This register is R/W to maintain software compatibility. These bits have no effect on
hardware.
8.1.25 SDMA_TIM—Synchronous DMA Timing Register (SATA–
D31:F2)
Address Offset: 4Ah–4Bh Attribute: R/W
Default Value: 0000h Size: 16 bits
Note: This register is R/W to maintain software compatibility. These bits have no effect on
hardware.
8.1.26 IDE_CONFIG—IDE I/O Configuration Register (SATA–
D31:F2)
Address Offset: 54h–57h Attribute: R/W
Default Value: 00000000h Size: 32 bits
Note: This register is R/W to maintain software compatibility. These bits have no effect on
hardware.
Bit Description
7:4 Reserved
3:0 SDMA_CNT Field 1 — R/W. This field is R/W to maintain software compatibility. This field has no
effect on hardware.
Bit Description
15:14 Reserved
13:12 SDMA_TIM Field 4— R/W. This field is R/W to maintain software compatibility. This field has no
effect on hardware.
11:10 Reserved
9:8 SDMA_TIM Field 3— R/W. This field is R/W to maintain software compatibility. This field has no
effect on hardware.
7:6 Reserved
5:4 SDMA_TIM Field 2— R/W. This field is R/W to maintain software compatibility. This field has no
effect on hardware.
3:2 Reserved
1:0 SDMA_TIM Field 1 — R/W. This field is R/W to maintain software compatibility. This field has no
effect on hardware.
Bit Description
31:24 Reserved
23:12 IDE_CONFIG Field 2 — R/W. This field is R/W to maintain software compatibility. This field has no
effect on hardware.
11:8 Reserved
7:0 IDE_CONFIG Field 1 — R/W. This field is R/W to maintain software compatibility. This field has no
effect on hardware.