Datasheet

SATA Controller Registers (D31:F2)
Intel® Xeon® Processor D-1500 Product Family 331
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
8.1.20 INT_LN—Interrupt Line Register (SATA–D31:F2)
Address Offset: 3Ch Attribute: R/W
Default Value: 00h Size: 8 bits
Function Level Reset:No
8.1.21 INT_PN—Interrupt Pin Register (SATA–D31:F2)
Address Offset: 3Dh Attribute: RO
Default Value: See Register Description Size: 8 bits
8.1.22 IDE_TIM—IDE Timing Register (SATA–D31:F2)
Address Offset: Primary: 40h–41h Attribute: R/W
Secondary: 42h–43h
Default Value: 0000h Size: 16 bits
Bits 14:12 and 9:0 of this register are R/W to maintain software compatibility. These
bits have no effect on hardware.
8.1.23 SIDETIM—Slave IDE Timing Register (SATA–D31:F2)
Address Offset: 44h Attribute: R/W
Default Value: 00h Size: 8 bits
Note: This register is R/W to maintain software compatibility. These bits have no effect on
hardware.
Bit Description
7:0 Interrupt Line — R/W. This field is used to communicate to software the interrupt line that the
interrupt pin is connected to.
Interrupt Line register is not reset by FLR.
Bit Description
7:0 Interrupt Pin — RO. This reflects the value of D31IP.SIP (Chipset Config Registers:Offset
3100h:bits 11:8).
Bit Description
15 IDE Decode Enable (IDE) — R/W. Individually enable/disable the Primary or Secondary decode.
0 = Disable.
1 = Enables Intel® Xeon® Processor D-1500 Product Family to decode the associated Command
Block (1F0–1F7h for primary,
170–177h for secondary, or their native mode BAR equivalents) and Control Block (3F6h for
primary, 376h for secondary, or their native mode BAR equivalents).
This bit effects the IDE decode ranges for both legacy and native-mode decoding.
14:12 IDE_TIM Field 2 — R/W. This field is R/W to maintain software compatibility. This field has no effect
on hardware.
11:10 Reserved
9:0 IDE_TIM Field 1 — R/W. This field is R/W to maintain software compatibility. This field has no effect
on hardware.
Bit Description
7:0 SIDETIM Field 1 — R/W. This field is R/W to maintain software compatibility. This field has no effect
on hardware.