Datasheet

SATA Controller Registers (D31:F2)
330 Intel® Xeon® Processor D-1500 Product Family
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
Note: The ABAR register must be set to a value of 0001_0000h or greater.
8.1.16.2 When SCC is 01h
When the programming interface is IDE, the register becomes an I/O BAR allocating
16 bytes of I/O space for the I/O-mapped registers defined in Section 8.2. Although 16
bytes of locations are allocated, only 8 bytes are used as SINDX and SDATA registers;
with the remaining 8 bytes preserved for future enhancement.
Address Offset: 24h–27h Attribute: R/WO
Default Value: 00000001h Size: 32 bits
8.1.17 SVID—Subsystem Vendor Identification Register (SATA–
D31:F2)
Address Offset: 2Ch–2Dh Attribute: R/WO
Default Value: 0000h Size: 16 bits
Lockable: No Power Well: Core
Function Level Reset:No
8.1.18 SID—Subsystem Identification Register (SATA–D31:F2)
Address Offset: 2Eh–2Fh Attribute: R/WO
Default Value: 0000h Size: 16 bits
Lockable: No Power Well: Core
Function Level Reset: No
8.1.19 CAP—Capabilities Pointer Register (SATA–D31:F2)
Address Offset: 34h Attribute: RO
Default Value: 80h Size: 8 bits
Bit Description
31:16 Reserved
15:4 Base Address (BA) — R/W. Base address of the I/O space.
3:1 Reserved
0 Resource Type Indicator (RTE) — RO. Indicates a request for I/O space.
Bit Description
15:0 Subsystem Vendor ID (SVID) — R/WO. Value is written by BIOS. No hardware action taken on
this value.
Bit Description
15:0 Subsystem ID (SID) — R/WO. Value is written by BIOS. No hardware action taken on this value.
Bit Description
7:0 Capabilities Pointer (CAP_PTR) — RO. Indicates that the first capability pointer offset is 80h. This
value changes to 70h if the Sub Class Code (SCC) (Dev 31:F2:0Ah) is configure as IDE mode (value
of 01).