Datasheet

SATA Controller Registers (D31:F2)
Intel® Xeon® Processor D-1500 Product Family 329
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
Note: This 4-byte I/O space is used in native mode for the Secondary Controller’s Control Block.
8.1.15 BAR—Legacy Bus Master Base Address Register (SATA–
D31:F2)
Address Offset: 20h–23h Attribute: R/W, RO
Default Value: 00000001h Size: 32 bits
The Bus Master IDE interface function uses Base Address register 5 to request a 16-
byte I/O space to provide a software interface to the Bus Master functions. Only 12
bytes are actually used (6 bytes for primary, 6 bytes for secondary). Only bits [15:4]
are used to decode the address.
8.1.16 ABAR/SIDPBA1—AHCI Base Address Register / Serial ATA
Index Data Pair Base Address (SATA–D31:F2)
When the programming interface is not IDE (that is, SCC is not 01h), this register is
named ABAR. When the programming interface is IDE, this register becomes SIDPBA.
Hardware does not clear those BA bits when switching from IDE component to non-IDE
component or vice versa. BIOS is responsible for clearing those bits to 0 since the
number of writable bits changes after component switching (as indicated by a change
in SCC). In the case, this register will then have to be re-programmed to a proper
value.
8.1.16.1 When SCC is not 01h
When the programming interface is not IDE, the register represents a memory BAR
allocating space for the AHCI memory registers defined in Section 8.4.
Address Offset: 24–27h Attribute: R/W, RO
Default Value: 00000000h Size: 32 bits
1Reserved
0 Resource Type Indicator (RTE) — RO. Hardwired to 1 to indicate a request for I/O space.
Bit Description
Bit Description
31:16 Reserved
15:5 Base Address — R/W. This field provides the base address of the I/O space (16 consecutive I/O
locations).
4 Base— R/W / RO. When SCC is 01h, this bit will be R/W resulting in requesting 16B of I/O space.
When SCC is not 01h, this bit will be Read Only 0, resulting in requesting 32B of I/O space.
3:1 Reserved
0 Resource Type Indicator (RTE) — RO. Hardwired to 1 to indicate a request for I/O space.
Bit Description
31:11 Base Address (BA) — R/W. Base address of register memory space (aligned to 2 KB)
10:4 Reserved
3 Prefetchable (PF) — RO. Indicates that this range is not pre-fetchable
2:1 Type (TP) — RO. Indicates that this range can be mapped anywhere in 32-bit address space.
0 Resource Type Indicator (RTE) — RO. Hardwired to 0 to indicate a request for register memory
space.