Datasheet

SATA Controller Registers (D31:F2)
Intel® Xeon® Processor D-1500 Product Family 327
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
8.1.6.3 When Sub Class Code Register (D31:F2:Offset 0Ah) = 06h
Address Offset: 09h Attribute: RO
Default Value: 01h Size: 8 bits
8.1.7 SCC—Sub Class Code Register (SATA–D31:F2)
Address Offset: 0Ah Attribute: RO
Default Value: See bit description Size: 8 bits
8.1.8 BCC—Base Class Code Register (SATA–D31:F2SATA–
D31:F2)
Address Offset: 0Bh Attribute: RO
Default Value: 01h Size: 8 bits
8.1.9 PMLT—Primary Master Latency Timer Register (SATA–
D31:F2)
Address Offset: 0Dh Attribute: RO
Default Value: 00h Size: 8 bits
8.1.10 HTYPE—Header Type Register (SATA–D31:F2)
Address Offset: 0Eh Attribute: RO
Default Value: 00h Size: 8 bits
Bit Description
7:0 Interface (IF) — RO.
Indicates that the SATA Controller is an AHCI HBA that has a major revision of 1.
Bit Description
7:0 Sub Class Code (SCC)
This field specifies the sub-class code of the controller, per the table below:
MAP.SMS (D31:F2:Offset
90h:bit 7:6) Value
SCC Register Value
00b 01h (IDE Controller)
01b 06h (AHCI Controller)
10b 04h (RAID Controller)
Bit Description
7:0 Base Class Code (BCC) — RO.
01h = Mass storage device
Bit Description
7:0 Master Latency Timer Count (MLTC) — RO.
00h = Hardwired. The SATA controller is implemented internally, and is not arbitrated as a PCI
device, so it does not need a Master Latency Timer.
Bit Description
7 Multi-function Device (MFD) — RO.
Indicates this SATA controller is not part of a multifunction device.
6:0 Header Layout (HL) — RO.
Indicates that the SATA controller uses a target device layout.