Datasheet

SATA Controller Registers (D31:F2)
Intel® Xeon® Processor D-1500 Product Family 325
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
8.1.3 PCICMD—PCI Command Register (SATA–D31:F2)
Address Offset: 04h–05h Attribute: RO, R/W
Default Value: 0000h Size: 16 bits
8.1.4 PCISTS — PCI Status Register (SATA–D31:F2)
Address Offset: 06h–07h Attribute: R/WC, RO
Default Value: 02B0h Size: 16 bits
Note: For the writable bits, software must write a 1 to clear bits that are set. Writing a 0 to
the bit has no effect.
Bit Description
15:11 Reserved
10 Interrupt Disable — R/W. This disables pin-based INTx# interrupts. This bit has no effect on MSI
operation.
0 = Internal INTx# messages are generated if there is an interrupt and MSI is not enabled.
1 = Internal INTx# messages will not be generated.
9 Fast Back to Back Enable (FBE) — RO. Hardwired to 0.
8 SERR# Enable (SERR_EN) — RO. Hardwired to 0.
7 Wait Cycle Control (WCC) — RO. Hardwired to 0.
6 Parity Error Response (PER) — R/W.
0 = Disabled. SATA controller will not generate PERR# when a data parity error is detected.
1 = Enabled. SATA controller will generate PERR# when a data parity error is detected.
5 VGA Palette Snoop (VPS) — RO. Hardwired to 0.
4 Postable Memory Write Enable (PMWE) — RO. Hardwired to 0.
3 Special Cycle Enable (SCE) — RO. Hardwired to 0.
2 Bus Master Enable (BME) — R/W. This bit controls the SATA controller’s ability to act as a master
for data transfers. This bit does not impact the generation of completions for split transaction
commands.
1 Memory Space Enable (MSE) — R/W / RO. Controls access to the SATA controller’s target memory
space (for AHCI). This bit is RO 0 when not in AHCI/RAID modes.
0 I/O Space Enable (IOSE) — R/W. This bit controls access to the I/O space registers.
0 = Disables access to the Legacy or Native IDE ports (both Primary and Secondary) as well as the
Bus Master I/O registers.
1 = Enable. The Base Address register for the Bus Master registers should be programmed before
this bit is set.
Bit Description
15 Detected Parity Error (DPE) — R/WC.
0 = No parity error detected by SATA controller.
1 = SATA controller detects a parity error on its interface.
14 Signaled System Error (SSE) — RO. Hardwired to 0.
13 Received Master Abort (RMA) — R/WC.
0 = Master abort not generated.
1 = SATA controller, as a master, generated a master abort.
12 Reserved — R/WC.
11 Signaled Target Abort (STA) — RO. Hardwired to 0.
10:9 DEVSEL# Timing Status (DEV_STS) — RO.
01 = Hardwired; Controls the device select time for the SATA controller’s PCI interface.
8 Data Parity Error Detected (DPED) — R/WC. For Intel® Xeon® Processor D-1500 Product Family,
this bit can only be set on read completions received from the bus when there is a parity error.
0 = No data parity error received.
1 = SATA controller, as a master, either detects a parity error or sees the parity error line asserted,
and the parity error response bit (bit 6 of the command register) is set.
7 Fast Back to Back Capable (FB2BC) — RO. Hardwired to 1.
6 Reserved