Datasheet

LPC Interface Bridge Registers (D31:F0)
322 Intel® Xeon® Processor D-1500 Product Family
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
7.10.19 GP_RST_SEL3—GPIO Reset Select Register
Offset Address: GPIOBASE +68h Attribute: R/W
Default Value: 00000000h Size: 32 bits
Lockable: Yes Power Well: Core for 0:7, 16:23,
Resume for 8:15, 24:31
14:8 GP_RST_SEL[46:40] — R/W.
0 = Corresponding GPIO registers will be reset by PWROK de-assertion, CF9h reset (06h or 0Eh), or
SYS_RESET# assertion.
1 = Corresponding GPIO registers will be reset by RSMRST# assertion only.
7:0 Reserved
Bit Description
Bit Description
31:12 Reserved
11:10 GP_RST_SEL[75:74] — R/W.
0 = Corresponding GPIO registers will be reset by PWROK de-assertion, CF9h reset (06h or 0Eh), or
SYS_RESET# assertion.
1 = Corresponding GPIO registers will be reset by RSMRST# assertion only.
9Reserved
8 GP_RST_SEL[72] — R/W.
0 = Corresponding GPIO registers will be reset by PWROK de-assertion, CF9h reset (06h or 0Eh), or
SYS_RESET# assertion.
1 = Corresponding GPIO registers will be reset by RSMRST# assertion only.
7:0 Reserved