Datasheet

LPC Interface Bridge Registers (D31:F0)
Intel® Xeon® Processor D-1500 Product Family 321
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
7.10.17 GP_RST_SEL1 — GPIO Reset Select Register
Offset Address: GPIOBASE +60h Attribute: R/W
Default Value: 01000000h Size: 32 bits
Lockable: Yes Power Well: Core for 0:7, 16:23,
Resume for 8:15, 24:31
7.10.18 GP_RST_SEL2—GPIO Reset Select Register
Offset Address: GPIOBASE +64h Attribute: R/W
Default Value: 00000000h Size: 32 bits
Lockable: Yes Power Well: Core for 0:7, 16:23,
Resume for 8:15, 24:31
11:0 GP_LVL[75:64] — R/W.
These registers are implemented as dual read/write with dedicated storage each. Write value will be
stored in the write register, while read is coming from the read register which will always reflect the
value of the pin. If GPIO[n] is programmed to be an output (using the corresponding bit in the
GP_IO_SEL register), then the corresponding GP_LVL[n] write register value will drive a high or low
value on the output pin.
1 = high, 0 = low.
When configured in native mode (GPIO_USE_SEL[n] is 0), writes to these bits are stored but have
no effect to the pin value. The value reported in this register is undefined when programmed as
native mode.
Notes:
If GPIO[n] does not exist, then, the (n-64) bit in this register will always read as 0 and
writes will have no effect.
Bit Description
Bit Description
31:24 GP_RST_SEL[31:24] — R/W.
0 = Corresponding GPIO registers will be reset by PWROK de-assertion, CF9h reset (06h or 0Eh), or
SYS_RESET# assertion.
1 = Corresponding GPIO registers will be reset by RSMRST# assertion only.
Note: GPIO[24] register bits are not cleared by CF9h reset by default.
23:16 Reserved
15:14 GP_RST_SEL[15:14] — R/W.
0 = Corresponding GPIO registers will be reset by PWROK de-assertion, CF9h reset (06h or 0Eh), or
SYS_RESET# assertion.
1 = Corresponding GPIO registers will be reset by RSMRST# assertion only.
13 Reserved
12:8 GP_RST_SEL[12:8] — R/W.
0 = Corresponding GPIO registers will be reset by PWROK de-assertion, CF9h reset (06h or 0Eh), or
SYS_RESET# assertion.
1 = Corresponding GPIO registers will be reset by RSMRST# assertion only.
7:0 Reserved
Bit Description
31 Reserved
30:25 GP_RST_SEL[62:57] — R/W.
0 = Corresponding GPIO registers will be reset by PWROK de-assertion, CF9h reset (06h or 0Eh), or
SYS_RESET# assertion.
1 = Corresponding GPIO registers will be reset by RSMRST# assertion only.
24:15 Reserved