Datasheet

LPC Interface Bridge Registers (D31:F0)
320 Intel® Xeon® Processor D-1500 Product Family
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
7.10.15 GP_IO_SEL3—GPIO Input/Output Select 3 Register
Offset Address: GPIOBASE +44h Attribute: R/W
Default Value: 00000FF0h Size: 32 bits
Lockable: Yes Power Well: Core for 0:7, 16:23,
Resume for 8:15, 24:31
This register corresponds to GPIO[75:64]. Bit 0 corresponds to GPIO64 and bit 11
corresponds to GPIO75.
7.10.16 GP_LVL3—GPIO Level for Input or Output 3 Register
Offset Address: GPIOBASE +48h Attribute: R/W
Default Value: 000000C0h Size: 32 bits
Lockable: Yes Power Well: Core for 0:7, 16:23,
Resume for 8:15, 24:31
This register corresponds to GPIO[75:64]. Bit 0 corresponds to GPIO64 and bit 11
corresponds to GPIO75.
11:0 GPIO_USE_SEL3[75:64]— R/W. Each bit in this register enables the corresponding GPIO (if it
exists) to be used as a GPIO, rather than for the native function.
0 = Signal used as native function.
1 = Signal used as a GPIO.
Notes:
1. The following bit is always 1 because it is always unmultiplexed: 8
2. If GPIO[n] does not exist, then, the (n-64) bit in this register will always read as 0 and writes will
have no effect.
3. After a full reset RSMRST# all multiplexed signals in the resume and core wells are configured
as their default function. After only a PLTRST#, the GPIOs in the core well are configured as
their default function.
4. When configured to GPIO mode, the multiplexing logic will present the inactive state to native
logic that uses the pin as an input.
Bit Description
Bit Description
31:12 Always 0. No corresponding GPIO.
11:0 GP_IO_SEL3[75:64]— R/W.
0 = GPIO signal is programmed as an output.
1 = Corresponding GPIO signal (if enabled in the GPIO_USE_SEL3 register) is programmed as an
input.
Notes:
If GPIO[n] does not exist, then, the (n-64) bit in this register will always read as 0 and
writes will have no effect.
Bit Description
31:12 Always 0. No corresponding GPIO.