Datasheet
LPC Interface Bridge Registers (D31:F0)
318 Intel® Xeon® Processor D-1500 Product Family
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
7.10.10 GPI_INV—GPIO Signal Invert Register
Offset Address: GPIOBASE +2Ch Attribute: R/W
Default Value: 00000000h Size: 32 bits
Lockable: No Power Well: Core for 17, 16, 7:0
7.10.11 GPIO_USE_SEL2—GPIO Use Select 2 Register
Offset Address: GPIOBASE +30h Attribute: R/W
Default Value: 020300FFh Size: 32 bits
Lockable: Yes Power Well: Core for 0:7, 16:23,
Resume for 8:15, 24:31
This register corresponds to GPIO[63:32].
Bit Description
31:16 Reserved
15:14 Input Inversion (GP_INV[n]) — R/W. This bit only has effect if the corresponding GPIO is used as
an input and used by the GPE logic, where the polarity matters. When set to ‘1’, then the GPI is
inverted as it is sent to the GPE logic that is using it. This bit has no effect on the value that is
reported in the GP_LVL register.
These bits are used to allow both active-low and active-high inputs to cause SMI# or SCI. In the S0
or S1 state, the input signal must be active for at least two PCI clocks to ensure detection by Intel®
Xeon® Processor D-1500 Product Family. In the S4, or S5 states the input signal must be active for
at least 2 RTC clocks to ensure detection. The setting of these bits has no effect if the corresponding
GPIO is programmed as an output. These bits correspond to GPI that are in the resume well, and will
be reset to their default values by RSMRST# or by a write to the CF9h register.
0 = The corresponding GPI_STS bit is set when Intel® Xeon® Processor D-1500 Product Family
detects the state of the input pin to be high.
1 = The corresponding GPI_STS bit is set when Intel® Xeon® Processor D-1500 Product Family
detects the state of the input pin to be low.
13 Reserved
12:0 Input Inversion (GP_INV[n]) — R/W. This bit only has effect if the corresponding GPIO is used as
an input and used by the GPE logic, where the polarity matters. When set to ‘1’, then the GPI is
inverted as it is sent to the GPE logic that is using it. This bit has no effect on the value that is
reported in the GP_LVL register.
These bits are used to allow both active-low and active-high inputs to cause SMI# or SCI. In the S0
or S1 state, the input signal must be active for at least two PCI clocks to ensure detection by Intel®
Xeon® Processor D-1500 Product Family. In the S4, or S5 states the input signal must be active for
at least 2 RTC clocks to ensure detection. The setting of these bits has no effect if the corresponding
GPIO is programmed as an output. These bits correspond to GPI that are in the resume well, and will
be reset to their default values by RSMRST# or by a write to the CF9h register.
0 = The corresponding GPI_STS bit is set when Intel® Xeon® Processor D-1500 Product Family
detects the state of the input pin to be high.
1 = The corresponding GPI_STS bit is set when Intel® Xeon® Processor D-1500 Product Family
detects the state of the input pin to be low.
Bit Description
31:0 GPIO_USE_SEL2[63:32]— R/W. Each bit in this register enables the corresponding GPIO (if it
exists) to be used as a GPIO, rather than for the native function.
0 = Signal used as native function.
1 = Signal used as a GPIO.
Notes:
1. The following bits are always 1 because they are always unmultiplexed: 3, 25. The following bit
is unmultiplexed and is also 1: 0.
2. If GPIO[n] does not exist, then, the (n-32) bit in this register will always read as 0 and writes
will have no effect.
3. After a full reset RSMRST# all multiplexed signals in the resume and core wells are configured
as their default function. After only a PLTRST#, the GPIOs in the core well are configured as
their default function.
4. When configured to GPIO mode, the multiplexing logic will present the inactive state to native
logic that uses the pin as an input.
5. Bit 26 is ignored, functionality is configured by bits 9:8 of FLMAP0 register.