Datasheet

LPC Interface Bridge Registers (D31:F0)
Intel® Xeon® Processor D-1500 Product Family 317
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
7.10.7 GP_SB_DATA—GP Serial Blink Data Register
Offset Address: GPIOBASE +24h Attribute: R/W
Default Value: 00000000h Size: 32 bits
Lockable: No Power Well: Core
7.10.8 GPI_NMI_EN—GPI NMI Enable Register
Offset Address: GPIOBASE +28h Attribute: R/W
Default Value: 00000h Size: 16 bits
Lockable: No Power Well: Core for 0:7
Resume for 8:15
7.10.9 GPI_NMI_STS—GPI NMI Status Register
Offset Address: GPIOBASE +2Ah Attribute: R/WC
Default Value: 00000h Size: 16 bits
Lockable: Yes Power Well: Core for 0:7
Resume for 8:15
7:1 Reserved
0 Go — R/W. This bit is set to 1 by software to start the serialization process. Hardware clears the bit
after the serialized data is sent. Writes of 0 to this register have no effect. Software should not write
this bit to 1 unless the Busy status bit is cleared.
Bit Description
Bit Description
31:0 GP_SB_DATA[31:0] — R/W. This register contains the data serialized out. The number of bits
shifted out are selected through the DLS field in the GP_SB_CMDSTS register. This register
should not be modified by software when the Busy bit is set.
Bit Description
15:14 GPI_NMI_EN[15:14]. GPI NMI Enable: This bit only has effect if the corresponding GPIO is
used as an input and its GPI_ROUT register is being programmed to NMI functionality. When set
to 1, it used to allow active-low and active-high inputs (depends on inversion bit) to cause NMI.
13 Reserved
12:0 GPI_NMI_EN[12:0]. GPI NMI Enable: This bit only has effect if the corresponding GPIO is
used as an input and its GPI_ROUT register is being programmed to NMI functionality. When set
to 1, it used to allow active-low and active-high inputs (depends on inversion bit) to cause NMI.
Bit Description
15:14 GPI_NMI_STS[15:14]. GPI NMI Status: GPI_NMI_STS[15:0]. GPI NMI Status: This bit is set
if the corresponding GPIO is used as an input, and its GPI_ROUT register is being programmed to
NMI functionality and also GPI_NMI_EN bit is set when it detects either:
1) active-high edge when its corresponding GPI_INV is configured with value 0.
2) active-low edge when its corresponding GPI_INV is configured with value 1.
Note: Writing value of 1 will clear the bit, while writing value of 0 have no effect.
13 Reserved
12:0 GPI_NMI_STS[12:0]. GPI NMI Status: GPI_NMI_STS[15:0]. GPI NMI Status: This bit is set if
the corresponding GPIO is used as an input, and its GPI_ROUT register is being programmed to
NMI functionality and also GPI_NMI_EN bit is set when it detects either:
1) active-high edge when its corresponding GPI_INV is configured with value 0.
2) active-low edge when its corresponding GPI_INV is configured with value 1.
Note: Writing value of 1 will clear the bit, while writing value of 0 have no effect.