Datasheet

LPC Interface Bridge Registers (D31:F0)
316 Intel® Xeon® Processor D-1500 Product Family
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
7.10.5 GP_SER_BLINK—GP Serial Blink Register
Offset Address: GPIOBASE +1Ch Attribute: R/W
Default Value: 00000000h Size: 32 bits
Lockable: No Power Well: Core for 0:7, 16:23,
Resume for 8:15, 24:31
7.10.6 GP_SB_CMDSTS—GP Serial Blink Command
Status Register
Offset Address: GPIOBASE +20h Attribute: R/W, RO
Default Value: 00080000h Size: 32 bits
Lockable: No Power Well: Core
Bit Description
31:14 GP_SER_BLINK[31:14] — R/W. The setting of this bit has no effect if the corresponding GPIO is
programmed as an input or if the corresponding GPIO has the GPO_BLINK bit set.
When set to a 0, the corresponding GPIO will function normally.
When using serial blink, this bit should be set to a 1 while the corresponding GP_IO_SEL bit is set to
1. Setting the GP_IO_SEL bit to 0 after the GP_SER_BLINK bit ensures Intel® Xeon® Processor D-
1500 Product Family will not drive a 1 on the pin as an output. When this corresponding bit is set to
a 1 and the pin is configured to output mode, the serial blink capability is enabled. Intel® Xeon®
Processor D-1500 Product Family will serialize messages through an open-drain buffer
configuration.
The value of the corresponding GP_LVL bit remains unchanged and does not impact the serial blink
capability in any way.
Writes to this register have no effect when the corresponding pin is configured in native mode and
the read value returned is undefined.
13 Reserved
12:0 GP_SER_BLINK[12:0] — R/W. The setting of this bit has no effect if the corresponding GPIO is
programmed as an input or if the corresponding GPIO has the GPO_BLINK bit set.
When set to a 0, the corresponding GPIO will function normally.
When using serial blink, this bit should be set to a 1 while the corresponding GP_IO_SEL bit is set to
1. Setting the GP_IO_SEL bit to 0 after the GP_SER_BLINK bit ensures Intel® Xeon® Processor D-
1500 Product Family will not drive a 1 on the pin as an output. When this corresponding bit is set to
a 1 and the pin is configured to output mode, the serial blink capability is enabled. Intel® Xeon®
Processor D-1500 Product Family will serialize messages through an open-drain buffer
configuration.
The value of the corresponding GP_LVL bit remains unchanged and does not impact the serial blink
capability in any way.
Writes to this register have no effect when the corresponding pin is configured in native mode and
the read value returned is undefined.
Bit Description
31:24 Reserved
23:22 Data Length Select (DLS) — R/W. This field determines the number of bytes to serialize on GPIO.
00 = Serialize bits 7:0 of GP_SB_DATA (1 byte)
01 = Serialize bits 15:0 of GP_SB_DATA (2 bytes)
10 = Undefined – Software must not write this value
11 = Serialize bits 31:0 of GP_SB_DATA (4 bytes)
Software should not modify the value in this register unless the Busy bit is clear. Writes to this
register have no effect when the corresponding pin is configured in native mode and the read value
returned is undefined.
21:16 Data Rate Select (DRS) — R/W. This field selects the number of 120ns time intervals to count
between Manchester data transitions. The default of 8h results in a 960 ns minimum time between
transitions. A value of 0h in this register produces undefined behavior.
Software should not modify the value in this register unless the Busy bit is clear.
15:9 Reserved
8 Busy — RO. This read-only status bit is the hardware indication that a serialization is in progress.
Hardware sets this bit to 1 based on the Go bit being set. Hardware clears this bit when the Go bit is
cleared by the hardware.