Datasheet

LPC Interface Bridge Registers (D31:F0)
Intel® Xeon® Processor D-1500 Product Family 315
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
7.10.4 GPO_BLINK—GPO Blink Enable Register
Offset Address: GPIOBASE +18h Attribute: R/W
Default Value: 00040000h Size: 32 bits
Lockable: No Power Well: Core for 0:7, 16:23,
Resume for 8:15, 24:31
Note: GPIO18 will blink by default immediately after reset. This signal could be connected to an LED to
indicate a failed boot (by programming BIOS to clear GP_BLINK18 after successful POST).
12:0 GP_LVL[12:0]— R/W. These registers are implemented as dual read/write with dedicated
storage each. Write value will be stored in the write register, while read is coming from the read
register which will always reflect the value of the pin.
If GPIO[n] is programmed to be an output (using the corresponding bit in the GP_IO_SEL
register), then the corresponding GP_LVL[n] write register value will drive a high or low value on
the output pin. 1 = high, 0 = low.
When configured in native mode (GPIO_USE_SEL[n] is 0), writes to these bits are stored but have
no effect to the pin value. The value reported in this register is undefined when programmed as
native mode.
Bit Description
Bit Description
31:14 GP_BLINK[31:14] — R/W. The setting of this bit has no effect if the corresponding GPIO
signal is programmed as an input.
0 = The corresponding GPIO will function normally.
1 = If the corresponding GPIO is programmed as an output, the output signal will blink at a
rate of approximately once per second. The high and low times have approximately 0.5
seconds each. The GP_LVL bit is not altered when this bit is set.
The value of the corresponding GP_LVL bit remains unchanged during the blink process, and
does not effect the blink in any way. The GP_LVL bit is not altered when programmed to blink. It
will remain at its previous value.
These bits correspond to GPIO in the Resume well. These bits revert to the default value based
on RSMRST# or a write to the CF9h register (but not just on PLTRST#).
13 Reserved
12:0 GP_BLINK[12:0] — R/W. The setting of this bit has no effect if the corresponding GPIO signal
is programmed as an input.
0 = The corresponding GPIO will function normally.
1 = If the corresponding GPIO is programmed as an output, the output signal will blink at a
rate of approximately once per second. The high and low times have approximately 0.5
seconds each. The GP_LVL bit is not altered when this bit is set.
The value of the corresponding GP_LVL bit remains unchanged during the blink process, and
does not effect the blink in any way. The GP_LVL bit is not altered when programmed to blink. It
will remain at its previous value.
These bits correspond to GPIO in the Resume well. These bits revert to the default value based
on RSMRST# or a write to the CF9h register (but not just on PLTRST#).