Datasheet

LPC Interface Bridge Registers (D31:F0)
314 Intel® Xeon® Processor D-1500 Product Family
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
7.10.2 GP_IO_SEL—GPIO Input/Output Select Register
Offset Address: GPIOBASE +04h Attribute: R/W
Default Value: EEFF6EFFh Size: 32 bits
Lockable: Yes Power Well: Core for 0:7, 16:23,
Resume for 8:15, 24:31
7.10.3 GP_LVL—GPIO Level for Input or Output Register
Offset Address: GPIOBASE +0Ch Attribute: R/W
Default Value: 02FE0100h Size: 32 bits
Lockable: Yes Power Well: Core for 0:7, 16:23,
Resume for 8:15, 24:31
12:0 GPIO_USE_SEL[12:0] — R/W. Each bit in this register enables the corresponding GPIO (if it exists)
to be used as a GPIO, rather than for the native function.
0 = Signal used as native function.
1 = Signal used as a GPIO.
Notes:
1. The following bits are always 1 because they are always unmultiplexed: 8, 15, 24, 27, and 28.
2. After a full reset (RSMRST#) all multiplexed signals in the resume and core wells are
configured as their default function. After only a PLTRST#, the GPIOs in the core well are
configured as their default function.
3. When configured to GPIO mode, the multiplexing logic will present the inactive state to native
logic that uses the pin as an input.
4. All GPIOs are reset to the default state by CF9h reset. Other resume well GPIOs' reset
behavior can be programmed using GP_RST_SEL registers.
Bit Description
Bit Description
31:14 GP_IO_SEL[31:14] — R/W.
When configured in native mode (GPIO_USE_SEL[n] is 0), writes to these bits have no effect. The
value reported in this register is undefined when programmed as native mode.
0 = Output. The corresponding GPIO signal is an output.
1 = Input. The corresponding GPIO signal is an input.
13 Reserved
12:0 GP_IO_SEL[12:0] — R/W.
When configured in native mode (GPIO_USE_SEL[n] is 0), writes to these bits have no effect. The
value reported in this register is undefined when programmed as native mode.
0 = Output. The corresponding GPIO signal is an output.
1 = Input. The corresponding GPIO signal is an input.
Bit Description
31:14 GP_LVL[31:14]— R/W. These registers are implemented as dual read/write with dedicated
storage each. Write value will be stored in the write register, while read is coming from the read
register which will always reflect the value of the pin.
If GPIO[n] is programmed to be an output (using the corresponding bit in the GP_IO_SEL
register), then the corresponding GP_LVL[n] write register value will drive a high or low value on
the output pin. 1 = high, 0 = low.
When configured in native mode (GPIO_USE_SEL[n] is 0), writes to these bits are stored but have
no effect to the pin value. The value reported in this register is undefined when programmed as
native mode.
13 Reserved