Datasheet
LPC Interface Bridge Registers (D31:F0)
Intel® Xeon® Processor D-1500 Product Family 313
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
7.10.1 GPIO_USE_SEL—GPIO Use Select Register
Offset Address: GPIOBASE + 00h Attribute: R/W
Default Value: B96BA1FFh Size: 32 bits
Lockable: Yes Power Well: Core for 0:7, 16:23,
Resume for 8:15, 24:31
20h–23h GP_SB_CMDSTS GP Serial Blink Command Status 00080000h R/W
24h–27h GP_SB_DATA GP Serial Blink Data 00000000h R/W
28h–29h GPI_NMI_EN GPI NMI Enable 0000h R/W
2Ah–2Bh GPI_NMI_STS GPI NMI Status 0000h R/WC
2Ch–2Fh GPI_INV GPIO Signal Invert 00000000h R/W
30h–33h GPIO_USE_SEL2 GPIO Use Select 2
020300FFh
R/W
34h–37h GP_IO_SEL2 GPIO Input/Output Select 2 1F57FFF4h R/W
38h–3Bh GP_LVL2 GPIO Level for Input or Output 2 A4AA0007h R/W
3Ch–3Fh — Reserved 0h —
40h–43h GPIO_USE_SEL3 GPIO Use Select 3 00000130h R/W
44h–47h GP_IO_SEL3 GPIO Input/Output Select 3 00000FF0h R/W
48h–4Bh GP_LVL3 GPIO Level for Input or Output 3 000000C0h R/W
4Ch–5Fh — Reserved — —
60h–63h GP_RST_SEL1 GPIO Reset Select 1 01000000h R/W
64h–67h GP_RST_SEL2 GPIO Reset Select 2 00000000h R/W
68h–6Bh GP_RST_SEL3 GPIO Reset Select 3 00000000h R/W
6Ch–7Fh — Reserved — —
Table 7-13. Registers to Control GPIO Address Map (Sheet 2 of 2)
GPIOBASE
+ Offset
Mnemonic Register Name Default Attribute
Bit Description
31:14 GPIO_USE_SEL[31:14] — R/W. Each bit in this register enables the corresponding GPIO (if it
exists) to be used as a GPIO, rather than for the native function.
0 = Signal used as native function.
1 = Signal used as a GPIO.
Notes:
1. The following bits are always 1 because they are always unmultiplexed: 8, 15, 24, 27, and 28.
2. After a full reset (RSMRST#) all multiplexed signals in the resume and core wells are
configured as their default function. After only a PLTRST#, the GPIOs in the core well are
configured as their default function.
3. When configured to GPIO mode, the multiplexing logic will present the inactive state to native
logic that uses the pin as an input.
4. All GPIOs are reset to the default state by CF9h reset. Other resume well GPIOs' reset
behavior can be programmed using GP_RST_SEL registers.
13 Reserved