Datasheet
LPC Interface Bridge Registers (D31:F0)
312 Intel® Xeon® Processor D-1500 Product Family
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
7.9.9 TCO_WDCNT—TCO Watchdog Control Register
Offset Address: TCOBASE + 0Eh Attribute: R/W
Default Value: 00h Size: 8 bits
Power Well: Resume
7.9.10 SW_IRQ_GEN—Software IRQ Generation Register
Offset Address: TCOBASE + 10h Attribute: R/W
Default Value: 03h Size: 8 bits
Power Well: Core
7.9.11 TCO_TMR—TCO Timer Initial Value Register
I/O Address: TCOBASE +12h Attribute: R/W
Default Value: 0004h Size: 16 bits
Lockable: No Power Well: Core
7.10 General Purpose I/O Registers
The control for the general purpose I/O signals is handled through a 128-byte I/O
space. The base offset for this space is selected by the GPIOBASE register.
Bit Description
7:0 The BIOS or system management software can write into this register to indicate more details on
the boot progress. The register will reset to 00h based on a RSMRST# (but not PLTRST#). The
external microcontroller can read this register to monitor boot progress.
Bit Description
7:2 Reserved
1 IRQ12_CAUSE — R/W. When software sets this bit to 1, IRQ12 will be asserted. When software sets
this bit to 0, IRQ12 will be de-asserted.
0 IRQ1_CAUSE — R/W. When software sets this bit to 1, IRQ1 will be asserted. When software sets
this bit to 0, IRQ1 will be de-asserted.
Bit Description
15:10 Reserved
9:0 TCO Timer Initial Value — R/W. Value that is loaded into the timer each time the TCO_RLD
register is written. Values of 0000h or 0001h will be ignored and should not be attempted. The timer
is clocked at approximately 0.6 seconds, and thus allows timeouts ranging from 1.2 second to
613.8 seconds.
Note: The timer has an error of ±1 tick (0.6 S).
The TCO Timer will only count down in the S0 state.
Table 7-13. Registers to Control GPIO Address Map (Sheet 1 of 2)
GPIOBASE
+ Offset
Mnemonic Register Name Default Attribute
00h–03h GPIO_USE_SEL GPIO Use Select B96BA1FFh R/W
04h–07h GP_IO_SEL GPIO Input/Output Select EEFF6EFFh R/W
08h–0Bh — Reserved 0h —
0Ch–0Fh GP_LVL GPIO Level for Input or Output 02FE0100h R/W
10h–13h — Reserved 0h —
14h–17h — Reserved 0h —
18h–1Bh GPO_BLINK GPIO Blink Enable 00040000h R/W
1Ch–1Fh GP_SER_BLINK GP Serial Blink 00000000h R/W