Datasheet
LPC Interface Bridge Registers (D31:F0)
Intel® Xeon® Processor D-1500 Product Family 311
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
7.9.7 TCO2_CNT—TCO2 Control Register
I/O Address: TCOBASE +0Ah Attribute: R/W
Default Value: 0008h Size: 16 bits
Lockable: No Power Well: Resume
7.9.8 TCO_MESSAGE1 and TCO_MESSAGE2 Registers
I/O Address: TCOBASE +0Ch (Message 1) Attribute: R/W
TCOBASE +0Dh (Message 2)
Default Value: 00h Size: 8 bits
Lockable: No Power Well: Resume
9 NMI2SMI_EN — R/W.
0 = Normal NMI functionality.
1 = Forces all NMIs to instead cause SMIs. The functionality of this bit is dependent upon the
settings of the NMI_EN bit and the GBL_SMI_EN bit as detailed in the following table:
8 NMI_NOW — R/WC.
0 = Software clears this bit by writing a 1 to it. The NMI handler is expected to clear this bit.
Another NMI will not be generated until the bit is cleared.
1 = Writing a 1 to this bit causes an NMI. This allows the BIOS or SMI handler to force an entry to
the NMI handler.
7:0 Reserved
Bit Description
NMI_EN GBL_SMI_EN Description
0b 0b No SMI# at all because GBL_SMI_EN = 0
0b 1b SMI# will be caused due to NMI events
1b 0b No SMI# at all because GBL_SMI_EN = 0
1b 1b No SMI# due to NMI because NMI_EN = 1
Bit Description
15:6 Reserved
5:4 OS_POLICY — R/W. OS-based software writes to these bits to select the policy that the BIOS will
use after the platform resets due the WDT. The following convention is recommended for the BIOS
and OS:
00 = Boot normally
01 = Shut down
10 = Do not load OS. Hold in pre-boot state and use LAN to determine next step
11 = Reserved
Note: These are just scratchpad bits. They should not be reset when the TCO logic resets the
platform due to Watchdog Timer.
3 GPIO11_ALERT_DISABLE — R/W. At reset (using RSMRST# asserted) this bit is set and GPIO[11]
alerts are disabled.
0 = Enable.
1 = Disable GPIO11/SMBALERT# as an alert source for the heartbeats and the SMBus slave.
2:1 INTRD_SEL — R/W. This field selects the action to take if the INTRUDER# signal goes active.
00 = No interrupt or SMI#
01 = Interrupt (as selected by TCO_INT_SEL).
10 = SMI
11 = Reserved
0Reserved
Bit Description
7:0 TCO_MESSAGE[n] — R/W. BIOS can write into these registers to indicate its boot progress. The
external microcontroller can read these registers to monitor the boot progress.