Datasheet

LPC Interface Bridge Registers (D31:F0)
310 Intel® Xeon® Processor D-1500 Product Family
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
7.9.6 TCO1_CNT—TCO1 Control Register
I/O Address: TCOBASE +08h Attribute: R/W, R/WLO, R/WC
Default Value: 0000h Size: 16 bits
Lockable: No Power Well: Core
2 BOOT_STS — R/WC.
0 = Cleared by Intel® Xeon® Processor D-1500 Product Family based on RSMRST# or by software
writing a 1 to this bit. Software should first clear the SECOND_TO_STS bit before writing a 1 to
clear the BOOT_STS bit.
1 = Set to 1 when the SECOND_TO_STS bit goes from 0 to 1 and the processor has not fetched the
first instruction.
If rebooting due to a second TCO timer timeout, and if the BOOT_STS bit is set, Intel® Xeon®
Processor D-1500 Product Family will reboot using the ‘safe’ multiplier (1111). This allows the
system to recover from a processor frequency multiplier that is too high, and allows the BIOS to
check the BOOT_STS bit at boot. If the bit is set and the frequency multiplier is 1111, then the BIOS
knows that the processor has been programmed to an invalid multiplier.
1 SECOND_TO_STS — R/WC.
0 = Software clears this bit by writing a 1 to it, or by a RSMRST#.
1 = Intel® Xeon® Processor D-1500 Product Family sets this bit to 1 to indicate that the TIMEOUT
bit had been (or is currently) set and a second timeout occurred before the TCO_RLD register
was written. If this bit is set and the NO_REBOOT config bit is 0, then Intel® Xeon® Processor
D-1500 Product Family will reboot the system after the second timeout. The reboot is done by
asserting PLTRST#.
0 Intruder Detect (INTRD_DET) — R/WC.
0 = Software clears this bit by writing a 1 to it, or by RTCRST# assertion.
1 = Set by Intel® Xeon® Processor D-1500 Product Family to indicate that an intrusion was
detected. This bit is set even if the system is in G3 state.
Notes:
1. This bit has a recovery time. After writing a 1 to this bit position (to clear it), the bit may be
read back as a 1 for up 65 microseconds before it is read as a 0. Software must be aware of this
recovery time when reading this bit after clearing it.
2. If the INTRUDER# signal is active when the software attempts to clear the INTRD_DET bit, the
bit will remain as a 1, and the SMI# will be generated again immediately. The SMI handler can
clear the INTRD_SEL bits (TCOBASE + 0Ah, bits 2:1), to avoid further SMIs. However, if the
INTRUDER# signals goes inactive and then active again, there will not be further SMI’s
(because the INTRD_SEL bits would select that no SMI# be generated).
3. If the INTRUDER# signal goes inactive some point after the INTRD_DET bit is written as a 1,
then the INTRD_DET signal will go to a 0 when INTRUDER# input signal goes inactive. This is
slightly different than a classic sticky bit, since most sticky bits would remain active indefinitely
when the signal goes active and would immediately go inactive when a 1 is written to the bit.
Bit Description
Bit Description
15:13 Reserved
12 TCO_LOCK — R/WLO. When set to 1, this bit prevents writes from changing the TCO_EN bit (in
offset 30h of Power Management I/O space). Once this bit is set to 1, it can not be cleared by
software writing a 0 to this bit location. A core-well reset is required to change this bit from 1 to 0.
This bit defaults to 0.
11 TCO Timer Halt (TCO_TMR_HLT) — R/W.
0 = The TCO Timer is enabled to count.
1 = The TCO Timer will halt. It will not count, and thus cannot reach a value that will cause an SMI#
or set the SECOND_TO_STS bit. When set, this bit will prevent rebooting and prevent Alert On
LAN event messages from being transmitted on the SMLink (but not Alert On LAN* heartbeat
messages).
10 Reserved