Datasheet

LPC Interface Bridge Registers (D31:F0)
Intel® Xeon® Processor D-1500 Product Family 309
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
7.9.5 TCO2_STS—TCO2 Status Register
I/O Address: TCOBASE +06h Attribute: R/WC
Default Value: 0000h Size: 16 bits
Lockable: No Power Well: Resume
(Except Bit 0, in RTC)
8 BIOSWR_STS — R/WC.
0 = Software clears this bit by writing a 1 to it.
1 = Intel® Xeon® Processor D-1500 Product Family sets this bit and generates and SMI# to
indicate an invalid attempt to write to the BIOS. This occurs when either:
a) The BIOSWP bit is changed from 0 to 1 and the BLD bit is also set, or
b) any write is attempted to the BIOS and the BIOSWP bit is also set.
Note: On write cycles attempted to the 4 MB lower alias to the BIOS space, the BIOSWR_STS will
not be set.
7 NEWCENTURY_STS — R/WC. This bit is in the RTC well.
0 = Cleared by writing a 1 to the bit position or by RTCRST# going active.
1 = This bit is set when the Year byte (RTC I/O space, index offset 09h) rolls over from 99 to 00.
Setting this bit will cause an SMI# (but not a wake event).
Note: The NEWCENTURY_STS bit is not valid when the RTC battery is first installed (or when RTC
power has not been maintained). Software can determine if RTC power has not been
maintained by checking the RTC_PWR_STS bit (D31:F0:A4h, bit 2), or by other means
(such as a checksum on RTC RAM). If RTC power is determined to have not been
maintained, BIOS should set the time to a valid value and then clear the NEWCENTURY_STS
bit.
The NEWCENTURY_STS bit may take up to 3 RTC clocks for the bit to be cleared after a 1 is written
to the bit to clear it. After writing a 1 to this bit, software should not exit the SMI handler until
verifying that the bit has actually been cleared. This will ensure that the SMI is not re-entered.
6:4 Reserved
3 TIMEOUT — R/WC.
0 = Software clears this bit by writing a 1 to it.
1 = Set by Intel® Xeon® Processor D-1500 Product Family to indicate that the SMI was caused by
the TCO timer reaching 0.
2 TCO_INT_STS — R/WC.
0 = Software clears this bit by writing a 1 to it.
1 = SMI handler caused the interrupt by writing to the TCO_DAT_OUT register (TCOBASE + 03h).
1 SW_TCO_SMI — R/WC.
0 = Software clears this bit by writing a 1 to it.
1 = Software caused an SMI# by writing to the TCO_DAT_IN register (TCOBASE + 02h).
0 NMI2SMI_STS — RO.
0 = Cleared by clearing the associated NMI status bit.
1 = Set by Intel® Xeon® Processor D-1500 Product Family when an SMI# occurs because an event
occurred that would otherwise have caused an NMI (because NMI2SMI_EN is set).
Bit Description
Bit Description
15:5 Reserved
4 SMLink Slave SMI Status (SMLINK_SLV_SMI_STS) — R/WC. Allow the software to go directly
into a pre-determined sleep state. This avoids race conditions. Software clears this bit by writing a 1
to it.
0 = The bit is reset by RSMRST#, but not due to the PCI Reset associated with exit from S4–S5
states.
1 = Intel® Xeon® Processor D-1500 Product Family sets this bit to 1 when it receives the SMI
message on the SMLink Slave Interface.
3Reserved