Datasheet

LPC Interface Bridge Registers (D31:F0)
308 Intel® Xeon® Processor D-1500 Product Family
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
7.9.2 TCO_DAT_IN—TCO Data In Register
I/O Address: TCOBASE +02h Attribute: R/W
Default Value: 00h Size: 8 bits
Lockable: No Power Well: Core
7.9.3 TCO_DAT_OUT—TCO Data Out Register
I/O Address: TCOBASE +03h Attribute: R/W
Default Value: 00h Size: 8 bits
Lockable: No Power Well: Core
7.9.4 TCO1_STS—TCO1 Status Register
I/O Address: TCOBASE +04h Attribute: R/WC, RO
Default Value: 2000h Size: 16 bits
Lockable: No Power Well: Core
(Except bit 7, in RTC)
9:0 TCO Timer Value — R/W. Reading this register will return the current count of the TCO timer.
Writing any value to this register will reload the timer to prevent the timeout.
Bit Description
Bit Description
7:0 TCO Data In Value — R/W. This data register field is used for passing commands from the OS to
the SMI handler. Writes to this register will cause an SMI and set the SW_TCO_SMI bit in the
TCO1_STS register (D31:F0:04h).
Bit Description
7:0 TCO Data Out Value — R/W. This data register field is used for passing commands from the SMI
handler to the OS. Writes to this register will set the TCO_INT_STS bit in the TCO1_STS register. It
will also cause an interrupt, as selected by the TCO_INT_SEL bits.
Bit Description
15:14 Reserved
13 TCO_SLVSEL (TCO Slave Select) — RO. This register bit is Read Only by Host and indicates the
value of TCO Slave Select Soft Strap. Refer to Intel® Xeon® Processor D-1500 Product Family Soft
Straps section of the SPI Chapter for details.
12 BDXSERR_STS — R/WC.
0 = Software clears this bit by writing a 1 to it.
1 = Intel® Xeon® Processor D-1500 Product Family received a special cycle message indicating
that it wants to cause an SERR#. The software must read the processor to determine the
reason for the SERR#.
11 Reserved
10 BDXSMI_STS — R/WC.
0 = Software clears this bit by writing a 1 to it.
1 = Intel® Xeon® Processor D-1500 Product Family received a special cycle message indicating
that it wants to cause an SMI. The software must read the processor to determine the reason
for the SMI.
9 BDXSCI_STS — R/WC.
0 = Software clears this bit by writing a 1 to it.
1 = Intel® Xeon® Processor D-1500 Product Family received a special cycle message indicating
that it wants to cause an SCI. The software must read to determine the reason for the SCI.