Datasheet

LPC Interface Bridge Registers (D31:F0)
306 Intel® Xeon® Processor D-1500 Product Family
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
7.8.3.14 ALT_GPI_SMI_EN2 - Alternate GPI SMI Enable 2 Register
I/O Address: PMBASE + 5Ch Attribute: R/W, RO
Default Value: 0000h Size: 16 bits
Lockable: No Usage: ACPI
Power Well: Suspend
7.8.3.15 ALT_GPI_SMI_STS2—Alternate GPI SMI Status 2 Register
I/O Address: PMBASE + 5E-5Fh Attribute: R/W, RO
Default Value: 00h Size: 16 bits
Lockable: No Usage: ACPI
Power Well: Suspend
0
Arbiter Disable (ARB_DIS) — R/W This bit is a scratchpad bit for legacy software compatibility.
Bit Description
Bit Description
15:8
Reserved
7 Alternate GPI[60] SMI Enable (ALT_GPI60_SMI_EN) — R/W. Refer to bit [0] in this register for
description.
6 Alternate GPI[57] SMI Enable (ALT_GPI57_SMI_EN) — R/W. Refer to bit [0] in this register for
description.
5 Reserved
4 Alternate GPI[43] SMI Enable (ALT_GPI43_SMI_EN) — R/W. Refer to bit [0] in this register for
description.
3 Alternate GPI[22] SMI Enable (ALT_GPI22_SMI_EN) — R/W. Refer to bit [0] in this register for
description.
2 Alternate GPI[21] SMI Enable (ALT_GPI21_SMI_EN) — R/W. Refer to bit [0] in this register for
description.
1 Alternate GPI[19] SMI Enable (ALT_GPI19_SMI_EN) — R/W. Refer to bit [0] in this register for
description.
0
Alternate GPI[17] SMI Enable (ALT_GPI17_SMI_EN) — R/W. These bits are used to enable the
corresponding GPIO to cause an SMI#. For these bits to have any effect, the following must be true.
• The corresponding bit in the ALT_GPI_SMI_STS2 register is set.
• The corresponding GPI must be routed in the GPI_ROUT2 register to cause an SMI.
• The corresponding GPIO must be implemented.
Bit Description
15:8
Reserved
7 Alternate GPI[60] SMI Status (ALT_GPI60_SMI_STS) - R/W. Refer to bit[0] in this register for
description.
6 Alternate GPI[57] SMI Status (ALT_GPI57_SMI_STS) - R/W. Refer to bit[0] in this register for
description.
5 Reserved
4 Alternate GPI[43] SMI Status (ALT_GPI43_SMI_STS) - R/W. Refer to bit[0] in this register for
description.
3 Alternate GPI[22] SMI Status (ALT_GPI22_SMI_STS) - R/W. Refer to bit[0] in this register for
description.
2 Alternate GPI[21] SMI Status (ALT_GPI21_SMI_STS) - R/W. Refer to bit[0] in this register for
description.
1 Alternate GPI[19] SMI Status (ALT_GPI19_SMI_STS) - R/W. Refer to bit[0] in this register for
description.