Datasheet

LPC Interface Bridge Registers (D31:F0)
Intel® Xeon® Processor D-1500 Product Family 305
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
7.8.3.12 DEVACT_STS—Device Activity Status Register
I/O Address: PMBASE +44h Attribute: R/WC
Default Value: 0000h Size: 16 bits
Lockable: No Usage: Legacy Only
Power Well: Core
Each bit indicates if an access has occurred to the corresponding device’s trap range, or
for bits 6:9 if the corresponding PCI interrupt is active. This register is used in
conjunction with the Periodic SMI# timer to detect any system activity for legacy power
management. The periodic SMI# timer indicates if it is the right time to read the
DEVACT_STS register (PMBASE + 44h).
Note: Software clears bits that are set in this register by writing a 1 to the bit position.
7.8.3.13 PM2_CNT—Power Management 2 Control Register
I/O Address: PMBASE + 50h Attribute: R/W
Default Value: 00h Size: 8 bits
Lockable: No Usage: ACPI
Power Well: Core
1 SWGPE_CTRL— R/W. This bit allows software to control the assertion of SWGPE_STS bit. This bit is
used by hardware as the level input signal for the SWGPE_STS bit in the GPE0_STS register. When
SWGPE_CTRL is 1, SWGPE_STS will be set to 1, and writes to SWGPE_STS with a value of 1 to clear
SWGPE_STS will result in SWGPE_STS being set back to 1 by hardware. When SWGPE_CTRL is 0,
writes to SWGPE_STS with a value of 1 will clear SWGPE_STS to 0.
In addition to being cleared by RSMRST# assertion, Intel® Xeon® Processor D-1500 Product Family
also clears this bit due to a Power Button Override event, Intel ME Initiated Power Button Override,
Intel ME Initiated Host Reset with Power down, SMBus unconditional power down, processor thermal
trip event, or due to an internal thermal sensor catastrophic condition.
0 Reserved
Bit Description
Bit Description
15:13 Reserved
12 KBC_ACT_STS — R/WC. KBC (60/64h).
0 = Indicates that there has been no access to this device I/O range.
1 = This device I/O range has been accessed. Clear this bit by writing a 1 to the bit location.
11:10 Reserved
9 PIRQDH_ACT_STS — R/WC. PIRQ[D or H].
0 = The corresponding PCI interrupts have not been active.
1 = At least one of the corresponding PCI interrupts has been active. Clear this bit by writing a 1 to
the bit location.
8 PIRQCG_ACT_STS — R/WC. PIRQ[C or G].
0 = The corresponding PCI interrupts have not been active.
1 = At least one of the corresponding PCI interrupts has been active. Clear this bit by writing a 1 to
the bit location.
7 PIRQBF_ACT_STS — R/WC. PIRQ[B or F].
0 = The corresponding PCI interrupts have not been active.
1 = At least one of the corresponding PCI interrupts has been active. Clear this bit by writing a 1 to
the bit location.
6 PIRQAE_ACT_STS — R/WC. PIRQ[A or E].
0 = The corresponding PCI interrupts have not been active.
1 = At least one of the corresponding PCI interrupts has been active. Clear this bit by writing a 1 to
the bit location.
5:0 Reserved
Bit Description
7:1
Reserved