Datasheet

LPC Interface Bridge Registers (D31:F0)
304 Intel® Xeon® Processor D-1500 Product Family
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
7.8.3.9 ALT_GPI_SMI_EN—Alternate GPI SMI Enable Register
I/O Address: PMBASE +38h Attribute: R/W
Default Value: 0000h Size: 16 bits
Lockable: No Usage: ACPI or Legacy
Power Well: Suspend
7.8.3.10 ALT_GPI_SMI_STS—Alternate GPI SMI Status Register
I/O Address: PMBASE +3Ah Attribute: R/WC
Default Value: 0000h Size: 16 bits
Lockable: No Usage: ACPI or Legacy
Power Well: Suspend
7.8.3.11 GPE_CNTL—General Purpose Control Register
I/O Address: PMBASE +42h Attribute: R/W
Default Value: 00h Size: 8 bits
Lockable: No Usage: ACPI or Legacy
Power Well: Bits 0–1, 3–7: Suspend
Bit 2: RTC
3 LEGACY_USB_STS — RO. This bit is a logical OR of each of the SMI status bits in the USB Legacy
Keyboard/Mouse Control Registers ANDed with the corresponding enable bits. This bit will not be
active if the enable bits are not set.
0 = SMI# was not generated by USB Legacy event.
1 = SMI# was generated by USB Legacy event.
2 BIOS_STS — R/WC.
0 = No SMI# generated due to ACPI software requesting attention.
1 = This bit gets set by hardware when a 1 is written by software to the GBL_RLS bit
(D31:F0:PMBase + 04h:bit 2). When both the BIOS_EN bit (D31:F0:PMBase + 30h:bit 2) and
the BIOS_STS bit are set, an SMI# will be generated. The BIOS_STS bit is cleared when
software writes a 1 to its bit position.
1:0 Reserved
Bit Description
Bit Description
15:0 Alternate GPI SMI Enable — R/W. These bits are used to enable the corresponding GPIO to cause
an SMI#. For these bits to have any effect, the following must be true.
• The corresponding bit in the ALT_GPI_SMI_EN register is set.
• The corresponding GPI must be routed in the GPI_ROUT register to cause an SMI.
• The corresponding GPIO must be implemented.
Note: Mapping is as follows: bit 15 corresponds to GPI15... bit 0 corresponds to GPI0. GPIO[13] is
not supported.
Bit Description
15:0 Alternate GPI SMI Status — R/WC. These bits report the status of the corresponding GPIOs.
0 = Inactive. Software clears this bit by writing a 1 to it.
1 = Active
These bits are sticky. If the following conditions are true, then an SMI# will be generated and the
GPE0_STS bit set:
• The corresponding bit in the ALT_GPI_SMI_EN register (PMBASE + 38h) is set
• The corresponding GPIO must be routed in the GPI_ROUT register to cause an SMI.
• The corresponding GPIO must be implemented.
Note: All bits are in the resume well. Default for these bits is dependent on the state of the GPIO
pins. GPIO[13] is not supported
Bit Description
7:2 Reserved