Datasheet

LPC Interface Bridge Registers (D31:F0)
Intel® Xeon® Processor D-1500 Product Family 303
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
16 SMBus SMI Status (SMBUS_SMI_STS) — R/WC. Software clears this bit by writing a 1 to it.
0 = This bit is set from the 64 kHz clock domain used by the SMBus. Software must wait at least
15.63 μs after the initial assertion of this bit before clearing it.
1 = Indicates that the SMI# was caused by:
1. The SMBus Slave receiving a message that an SMI# should be caused, or
2. The SMBALERT# signal goes active and the SMB_SMI_EN bit is set and the
SMBALERT_DIS bit is cleared, or
3. The SMBus Slave receiving a Host Notify message and the HOST_NOTIFY_INTREN and the
SMB_SMI_EN bits are set, or
4. Intel® Xeon® Processor D-1500 Product Family detecting the SMLINK_SLAVE_SMI command
while in the S0 state.
15 SERIRQ_SMI_STS — RO.
0 = SMI# was not caused by the SERIRQ decoder.
1 = Indicates that the SMI# was caused by the SERIRQ decoder.
Note: This is not a sticky bit
14 PERIODIC_STS — R/WC. Software clears this bit by writing a 1 to it.
0 = Software clears this bit by writing a 1 to it.
1 = This bit is set at the rate determined by the PER_SMI_SEL bits. If the PERIODIC_EN bit
(PMBASE + 30h, bit 14) is also set, Intel® Xeon® Processor D-1500 Product Family generates
an SMI#.
13 TCO_STS — R/WC. Software clears this bit by writing a 1 to it.
0 = SMI# not caused by TCO logic.
1 = Indicates the SMI# was caused by the TCO logic. This is not a wake event.
12 Device Monitor Status (DEVMON_STS) — RO.
0 = SMI# not caused by Device Monitor.
1 = Set if bit 0 of the DEVACT_STS register (PMBASE + 44h) is set. The bit is not sticky, so writes to
this bit will have no effect.
11 Microcontroller SMI# Status (MCSMI_STS) — R/WC. Software clears this bit by writing a 1 to it.
0 = Indicates that there has been no access to the power management microcontroller range (62h
or 66h).
1 = Set if there has been an access to the power management microcontroller range (62h or 66h)
and the Microcontroller Decode Enable #1 bit in the LPC Bridge I/O Enables configuration
register is 1 (D31:F0:Offset 82h:bit 11). This implementation assumes that the Microcontroller
is on LPC. If this bit is set, and the MCSMI_EN bit is also set, Intel® Xeon® Processor D-1500
Product Family will generate an SMI#.
10 GPE1_STS — RO. This bit is a logical OR of the bits in the ALT_GPI_SMI_STS and the
ALT_GPI_SMI_STS2 registers that are also set up to cause an SMI# (as indicated by the GPI_ROUT
and GPI_ROUT2 registers) and have the corresponding bit set in the ALT_GPI_SMI_EN and
ALT_GPI_SMI_EN2 registers. Bits that are not routed to cause an SMI# will have no effect on this
bit.
0 = SMI# was not generated by a GPI assertion.
1 = SMI# was generated by a GPI assertion.
9 GPE0_STS — RO. This bit is a logical OR of the bits 35, 13, 11, 10, 8 and 2 in the GPE0_STS register
(PMBASE + 28h) that also have the corresponding bit set in the GPE0_EN register (PMBASE + 2Ch).
0 = SMI# was not generated by a GPE0 event.
1 = SMI# was generated by a GPE0 event.
8 PM1_STS_REG — RO. This is an ORs of the bits in the ACPI PM1 Status Register (offset
PMBASE+00h) that can cause an SMI#.
0 = SMI# was not generated by a PM1_STS event.
1 = SMI# was generated by a PM1_STS event.
7 Reserved
6 SWSMI_TMR_STS — R/WC. Software clears this bit by writing a 1 to it.
0 = Software SMI# Timer has Not expired.
1 = Set by the hardware when the Software SMI# Timer expires.
5 APM_STS — R/WC. Software clears this bit by writing a 1 to it.
0 = No SMI# generated by write access to APM Control register with APMCH_EN bit set.
1 = SMI# was generated by a write access to the APM Control register with the APMC_EN bit set.
4 SLP_SMI_STS — R/WC. Software clears this bit by writing a 1 to the bit location.
0 = No SMI# caused by write of 1 to SLP_EN bit when SLP_SMI_EN bit is also set.
1 = Indicates an SMI# was caused by a write of 1 to SLP_EN bit when SLP_SMI_EN bit is also set.
Bit Description